SU1372615A1 - Frequency divider with variable fractional count-down ratio - Google Patents

Abstract

The invention relates to a pulse technique and can be used in digital frequency synthesizers. The aim of the invention is to expand the frequency range of the frequency divider while maintaining the minimum phase deviation of the output pulse sequence. For this purpose, the address counter 8, a constant one, is additionally entered in the frequency divider; the memory device 9, the switch 10 and the matrix 12. In addition, the frequency divider contains divider 1 with a variable division factor (CD), counters 2 and 3 , input bus 4, output bus 5, matrices 6 and 7 for selecting the integer part of the CD, matrix 11 for choosing the denominator of the CD. Matrix 12 is used to change the CD. The sampling time of values from ROM 9 does not depend on the CD, i.e. Changing the CD divider 1 does not depend on the frequency divider CD. 2il. i (L

Description

The device works as follows.

The output pulse sequence is formed from the input sequence due to the fact that the device passes only a fraction of the input sequence pulses to the output; the interval between the output pulses during the division process varies depending on the CD.

(1) (P + 1) ... (P + 1)

50

m

55

Step 1. Consider as correlation ts, between themselves the repetition factors s t. If with t, then consider

 cm

Dribe - if s: t, then -. ms

Let with t, then the fraction can be represented as

  F

m m

. i (k) F

13726154

This shows that the CD (P-t-1) is pov (F + 1) KD R ez F KD P, i.e.

Step 2. Consider now how the repetition factors k and d are related to each other.

Let k d, then

k Н (N + 1) Н + N (g - п)

". : f - 3 ...... "

di4

gg

and so on, until the numerator of the fraction in question or the difference between the denominator and the numerator is equal to one.

If c m, then the initial setting of the CD divider 1 is set equal to P, if c "t, then (P 1).

5 19 18 18 18 18 19 18 18

In this case, using matrices 6 and 7, set the divider CD 1, equal to 18. The number of 9 ROMs should be at least 16. We program ROM 9 so that 5, 10 and 16 cells have Log.1, and in the remaining cells - Log.O. With matrix 11, the conversion factor of counter 8 is 16. Switch 10 connects the required bit of ROM 9 to matrix 6 and switches only when the CD is changed. The switch 10 is controlled by the matrix li. In general, ROM 9 is programmed with k CD.

The operation of the device begins with the task using the matrices 6 and 7 of the whole part of the CD divider 1, using the matrix 11 denominators of the CD and using the matrix 12 of the desired bit ROM 9.

The input frequency pulses go to bus 4, and the pulses from the output of divider 1 go to bar 5, to the write inputs of counters 2 and 3, and to the counting input of the counter 8 pulses. The latter enumerates the addresses of the ROM 9 and, depending on the information recorded in it, the CD divider 1 changes.

Example. Let CD equal

291 3

-77 or 18 77- Then KD 19 divider 1 ID ID

will be repeated 3 times, and KD 18 divider 1-13 times in one counting cycle, equal to 291 periods of input pulses.

Using the above algorithm for the distribution of CD, get the CD divider 1 in the final form, which will vary as follows:

10 1916 19

19 18 18 18 18 18 19

PREMI R 2. Let set the CD

3 43 devices CD 5 o or -. This is value in

It means that when a sequence of 43 pulses is applied to the device input, 13 pulses are received at the device output with minimal phase deviation. The sequence of alternating CD divider 1 looks like a slouch.

55655656 2 57

Divisor 1 consists of just one counter 2, which provides division by integer coefficients 5 and 6.

Using the matrix 6, the CD divider 1 is set to 5. The outputs of the matrix 6 are connected to the information outputs of counter 2 in such a way that the first output of matrix 6 is connected to the information input of the lower bit of counter 2, and the last one - with the information input of the high bit of the counter 2

Using matrix 11, the coefficient is re-scaled of counter 8 to 8, i.e. equal to

,- ten

20

513726

denominator of the original CD. To implement a VD - "- it will require 8 ROM cells

about

9. In accordance with the sequence of alternating CD divider 1, the ROM 9 is programmed in such a way that Log.1 will be recorded in the second, fifth, and seventh cells of the ROM.

It is assumed that this CD is pea using the first bit of the ROM 9, then using the matrix 12, the control code of the switch 10 is set so that the information recorded in the first bit in the ROM 9 is fed to the output of the switch 10, and therefore input matrix 6. (Matrices 6, 7, 11, and 12 have input buses for inputting input data).

Consider the operation of the device during one cycle of frequency division by the device. Pulses are extracted from the sequence of input pulses (Fig. 2a) 25 43 and, for convenience, they are numbered. Before the arrival of the first pulse, the counter 8 is in the initial state, i.e. on bits Qi-Q-i (Fig. 2b, d, e) are Log.O. After the fifth input pulse, the first pulse (fig.2b) appears at the output of divider 1, which is fed to the input of counter 8 and to the record input of counter 2. Counter 8 changes its state, and counter 2 rewrites the CD equal to 35 5. After the arrival of the tenth input pulse, a second pulse appears at the output of divider 1, which changes the state of counter 8. From this, .. new address from ROM 9 is read Log.1 (FIG. 2e), which through the switch 10 is fed to the input of the matrix 6. Now in the matrix 6 a CD equal to 6 is recorded. Counter 2 rewrites this CD. The next output voltage pulse 1, the third one, appears after the sixteenth input pulse. Counter 8 changes its state and a Log.O. appears at the input of the matrix. Thus, matrix 6 again sets the CD to 5 and counter 2 overwrites this CD.

45

0

0

26

five

5 5

..

five

156

Fourth output pulse divider

1 does not change the counter's CD 2. Counter

2 changes CD only after the fifth and seventh output pulses. The forty-third input pulse causes the appearance of the eighth output pulse, which returns the counter B to its initial state. The process then repeats.

As a result, eight pulses with minimal phase deviation are obtained at the output of divider 1 (FIG. 2b).

The sampling time of the values of the ROM 9 with this construction of the device is constant and does not depend on the CD, i.e. change CD divider 1 does not depend on the CD device.

Claims (1)

Invention Formula A frequency divider with a fractional variable division factor, containing the first and second pulse counters connected in series, the counting input of the first of which is connected to the input bus, and the transfer output of the second and recording inputs of the first and second pulse counters - with the output bus, informational strokes of the first and second counters The pulses are connected to the outputs of the first and second matrices, respectively, and the control of the 1st and 1st inputs of which are connected to the corresponding control buses, which is different. so that, in order to expand the frequency range, an address counter, a persistent storage device, a switch, a third and a fourth matrix, whose control inputs are connected to the corresponding control buses, are entered, and the outputs, respectively, with the information inputs of the address counter and with the inputs control switch, the output of which is connected to the auxiliary input of the first matrix, the information inputs are connected to the outputs of the permanent storage device, the address inputs of which are connected to the codes of the counter and the address, the counting input of which is connected to the output bus. 431 5 10 15 20 25 30 35 0 I / I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I FIG. 2