SU1370644A1 - Time interval-to-code converter - Google Patents

Abstract

The invention relates to a pulse technique and can be used in systems for the temporal analysis of signals randomly distributed in time. The purpose of the invention, the expansion of the conversion range, is achieved by adapting to the intensity of the input signal flow. For this, a pulse counter 6, an analysis block 7 and a second random access memory (RAM) 10 are additionally entered into the device. In addition, the converter contains a crystal oscillator 1, a registration block 2, an input information bus 3, a buffer register 4, the first RAM 5, a block 8 control, input start 9 and address counter 11 In the converter, RAM is used more efficiently with changes in the flow rate of the input signals, and as a result, the recording range increases. 2 hp f-ly, 4 ill. i cl

Description

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The invention relates to a pulse technique and can be used in systems for the temporal analysis of signals randomly distributed in time.

The purpose of the invention is to expand the conversion range by adapting to the intensity of the stream of input signals.

FIG. 1 shows a block diagram of a time converter to the code in FIG. 2 a diagram of a converter analysis unit; in fig. 3 is a diagram of the converter registration unit in FIG. 4 is a control block diagram.

The time converter into the code contains a crystal oscillator 1, registration unit 2, input information bus 3, buffer register 4, first operational memory (RAM) 5 of the exact result, pulse counter 6, analysis unit 8, control unit 8, input 9 Start, the second RAM 10 rough result and the counter 11 addresses. The output of the crystal oscillator 1 is connected to the first input of registration unit 2, the second input of which is connected to the information bus 3, and the control output to the counting input of counter 6, the recording input of the buffer register 4 and the first input of the analysis unit 7, the second input of which is connected to the output of the first information bit of the registration unit 2, the output of the analysis unit 7 is connected to the second input of the control unit 8, the first input of which is connected to the input start bus 9, and the output is connected to the write control inputs of RAM 5 and 10 and the counter input of the 11 addr counter ca information outputs of which are connected to the address inputs of the RAM 10 and 5, the data inputs of which latter through buffer register 4 are connected to information outputs of block 2, registration, and data inputs of RAM 10 are connected to data outputs of the counter 6.

The analysis unit 7 consists of a delay element 12, an inverter 13, an EXCLUSIVE OR 14 element with an inversion, D-flip-flops 15 and 16 of the one-oscillator 17 and an AND 18 element. The D-input of the D-flip-flop 15 is connected to the bus O, C-to - with the first input of the analysis unit, the C-input of the D-flip-flop 16 and the input of the one-vibrator 1 7, and the S-input - with the output of the EXCLUSIVE OR 14 element with inversion, one of the inputs of which is directly, the second through the serially connected delay element 12 and the inverter 13 connected to the second input of the analysis unit, the output of which is connected to the output element And 18, one of the inputs to expensively connected to

10 to the output of the one-shot 17, and the second to the direct output of the D-flip-flop 16, the D-input of which is connected to the direct output of the D-flip-flop 15.

The registration block 2 contains a score - 15 whose trigger is 19 cf by the counting input,

the shift register 20 and the counter 21. The first input of the registration unit 2 is connected to the counting input of the counter 21 and the clock input of the register 20, the information input of which is connected to the output of the counting trigger 19, the counting input of which is connected to the second input of the registration unit 2,

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whose information outputs are connected to the information outputs of the shift register 20, and the high bit output of the counter 21 is connected to the control output of the registration unit 2.

30 The control unit 8 (Fig. 4) includes a cycle counter 22, a trigger 23, and an AND 24 element. The first input of the control unit is connected to the S input of the trigger 23, whose R input

-jg is connected to the overflow output of counter 22 cycles, the counting input of which is connected to the second input of the control unit and the first input of the AND 24 element, the second input of which is connected to the direct output of the trigger 23, and the output is connected to the output of the control unit 8.

The Converter operates as follows.

4g On the Start signal coming from the input bus 9 of the converter to the first input of the control unit 8, the trigger 23 is set to one, unlocking the AND 24 element

and ensuring the passage of pulses from the output of the analysis block 7 to the recording control inputs of RAM 5 and 10 and the counting input of the address counter 11.

If it is necessary to tie in the moments of arrival of the input pulses at the moment of the converter start-up by the pulse. Start it is necessary to reset the counter 21 of the registration unit 2, counter 6,

register 20 and counter 22 cycles of control block 8. The input information signals from the input bus 3 are fed to the second input of the registration unit 2, to the first input of which the pulses of the quartz oscillator 1 with the following period I are supplied. The registration unit 2 forms the scale of the exact result of the conversion and fixes the moment of arrival of the input signal by changing the code combination at the outputs of the shift register 20. In addition, the registration unit 2 forms time marks on the control output, followed by a period T p (where n is the capacity of the 1-bit counter 21), forming a rough conversion result and controlling the recording of information in the buffer register 4.

When the input pulse arrives at the registration unit 2, the counting trigger switches to the opposite state, resulting in a change in the code combination in the register 20. When the trigger 19 is set to one, the information input of the shift register is fed to the unit level and the contents of the code combination in the register the clock pulses change from the previous (zero) state to one. The fixahda of the moment of arrival of the input pulse is carried out at the time of changing the code

Combinations in register 20 from 1 to O or from O to 1.

The number of bits n of the register 20 is chosen to be equal to the capacity of the counter 21, i.e. n 2. Thus, the arrival of each of the pulses at the input of the converter is recorded by successively changing the code combination in the register.

The code combination formed at the output of the 20 n-bit register, which carries information about the arrival times of the input pulses, is fed through the information outputs of the registration unit 2 to the information inputs of the buffer register 4. The control pulses generated at the output of the registration unit 2 record information from the outputs of the shift register in the buffer register 4, regardless of its content.

The analysis unit allows you to determine whether a receipt is recorded

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of the input signal during the time interval n. If at least one input signal is registered, then during the next interval of duration n, analysis block 7 generates a write pulse with a duration t at the output. PS, which through block 8

The control is fed to the resolution inputs of RAM 5 and 10. This pulse ensures that the contents of the buffer register 4 and counter 6 are overwritten into the corresponding RAM and an exact and coarse conversion result is generated. In addition, on the falling edge of this pulse, the address counter 11 sets the next address code to the address inputs of RAM 5 and 10. Information is recorded synchronously changing information in the buffer register 4 and in the counter 6 "

Information about the arrival times of the input signals is accumulated in two arrays. Rough result

5 is generated by binary encoding and stored in RAM 10, and the result of the exact conversion stored in RAM 5 is encoded with a code requiring modulo-2 processing for every two adjacent bits.

The unit of analysis works as follows.

When changing the logic level at the second input of the analysis unit 7 (from O to 1 or from 1 to O), a short output pulse is formed at the output of the EXCLUSIVE OR element with inversion. The duration of this pulse is determined by the choice of the delay time of the delay element 12, taking into account the reliable switching of the trigger 15 via the S input to state 1. At the same time, the pulse difference from O to 1 arrives at the first

5, the input of the analysis unit 7, the trigger 16 switches to the single state, the one-shot 17 is started and the trigger state 15 is switched to the zero state. At this, the And 18 element is unlocked and transmits a pulse from the output of the one-shot 17 to the output of the analysis block 7. If during the interval.

equal to n t, the change of the logic voltage level at the second input of the registration unit did not occur, then no pulse is generated at its output. Input information pulses from the second input of block 2 are fed to the account 5

nineteen,

now the trigger input IV, the output of which is connected to the information input of the shift register 20. For each clock pulse arriving at the first input of the registration unit, the output state of the counting trigger 19 is recorded into the shift register 20. The change of state of the counting trigger 19 at the moments of arrival of the input pulses is fixed in the shift register 20, thereby implementing the time scale generator and fixing its state at the time of the event.

Due to the fact that the converter analyzes the presence of input signals during the registration cycle and, based on this analysis, controls the rewriting of information from the recording unit into RAM 5 and 10, it is possible to use RAM more efficiently with changes in the flow rate of the input signals and, as a result , increase the registration range.

Claims (3)

1. A time converter into a code containing a crystal oscillator, a registration unit, a buffer register, the first random access memory, an address counter, a control unit, the output of the crystal oscillator is connected to the first input of the registration unit, the second input of which is connected to the data input bus, and The output output is connected to the write input of the buffer register, the first input of the control unit is connected to the input bus Start, the output of the control unit is connected to the counting input of the address counter, the information outputs to Connected to the inputs of the addresses of the first random access memory, the information inputs of which are connected via a buffer register to the information outputs of the registration unit, characterized in that, in order to expand the conversion range by adapting to the intensity of the input signal flow, a second pulse is entered into it memory device, analysis unit, with the control output of the register unit 1370644 five 0 five 0 five 0 five 0 five connected to the counting input of the pulse counter and the first input of the analysis unit, the second input of which is connected to the output of the first information bit of the registration unit, and the output connected to the second input of the control unit whose output is connected to the recording inputs of the first and second operational memory the last of which is connected to the information outputs of the address counter, and the information inputs of the second random access memory are connected to the information outputs of the pulse counter . 2. The converter according to claim 1, characterized in that the analysis block contains a delay element, a NO element, an EXCLUSIVE OR element with an inversion, the first and second D-flip-flops, a one-shot and the AND element, the first input of the analysis block connected to the clock the inputs of the first and second D-flip-flops and the input of the single-vibrator, and the second input of the analysis unit is connected to the first input of the EXTRACT OR element with inversion directly, and to the second input through the serially connected delay element and the element NOT, and the output of the EXCLUSIVE OR element with inversion comm with the S-input of the first D-flip-flop, the D-input of which is connected to the logic zero bus, and the output is connected to the D-input of the second D-flip-flop, the output of which is connected to the first input of the And element, the second input of which is connected to the one-shot output - pa, and the output element And is connected to the output of the analysis unit. 3. The converter according to claim 1, which is characterized in that the registration unit contains a counting trigger, a shift register and a pulse counter, the first input of the registration block being connected to the counting input of the pulse counter and the clock input of the shift register, and the second input of the block is connected to the counting input of the counting trigger, the output of which is connected with the information input of the shift register, the information outputs of which are information outputs of the registration unit, and the high-order output of the pulse counter is the output of the registration unit. FIG. g (one} (2} nineteen fig.Z 21 20 deig " 22 w .: 2J