SU1363295A1 - Apparatus for representing the computation process - Google Patents

Abstract

The invention relates to computing and can be used to control the computing process in a computer. The aim of the invention is to expand the functionality of the device by providing a display of non-repeating or rarely repeating / program sections. The device contains a digital-to-step converter 1, an indication unit 2, switches 3, 4, 5, a counter 6, comparison circuits 7, 8, 11, a control unit 9, a generator of 10 clock pulses, an indication unit 12. The device allows you to display rarely repeated and non-repeating sections of programs and individual commands. .1 hp f-ly, 2 ill. 00, C5 CO GO (G

Description

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The invention relates to computing and can be used to control the course of a computing process in a computer.

The aim of the invention is to improve the functionality of the device by providing a display of non-repeating or rarely repeating program sections.

Fig, 1 shows a block diagram of the device; Fig. 2 is a control block diagram.

The device contains a digital-to-analog converter I, the first display unit 2, the first 3, the third 4 and the second 5 switches, the counter-6, the first 7 and the second 8 of the comparison circuit, the control unit 9, the clock generator 10, the third reference circuit 11 and the second block 12 indications

The control unit contains two groups of switches 13 and 14, switches 15-19, elements AND 20-22, triggers 23 and 24, elements OR 25-21, and delay element 28.

The device works as follows,

In the self-control mode, the devices through the outputs 3 and 4 of block 9 formed using switches 15 and 16 control signals through the third and fourth outputs, respectively, to the first inputs of switches 3 and 4, the latter being set respectively to their first groups. the inlet is connected to their outlet groups. The initial state of the switch 5 corresponds to the position when its group of outputs is associated with its second group of inputs (provided by a signal arriving at the first input of this switch from the output of the trigger 23 /. Pressing the switch 17 returns to the initial state. This opens

element 22 and sync pulses from generator 10 to the first input of block 9 pass through its perisal output to the second input of counter 6 and to the first inputs of trigger 24 and 23, switch 18 is set to depressed state (device self-monitoring mode) , On the dial fields of the switches 13 and 14, the i control binary codes of the addresses of the beginning and end of the program section, respectively, are fixed. In this case, the address code

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from the input field of switches 13 through the first group of outputs of block 9 enters the group of inputs of the counter 6 and the first group of inputs of the first comparison circuit 7 and the second switch 4, the code of the start address also enters the second group of inputs of the comparison circuit 7 through the group of outputs of the third Koi-iMyTaTopa 5, connected through its second group of inputs to the group of outputs of the second switch 4, the code of the address of the end of the dialer field of the switches 14 through the second group of outputs of the block 9 goes to the first group of inputs of the second comparison circuit 8. By pressing the switch 19, the device is started. In this case, the clock pulses through the first

0 the input of block 9 and through its sixth output go to the inputs of the first 7, second 8 and third 11 comparison circuits. As a result, the output of the first comparison circuit 7 produces a signal arriving at the second input of control unit 9. The signal received at the second input of block 9, through elements 21 and 27 switches trigger 24 and opens element 20, passes the clock pulses through the second output of block 9 to the counting input of counter 6. The binary code that changes as a result of the count through counter 6 comes to the first group of inputs of the switch 3 and then through its group of outputs to the group of inputs of the digital-to-threshold pre-. former I, the result of the conversion is displayed on the indication unit 2. The signal received at the second input of block 9 through the third element 26 OR, through the seventh output of block 9 and through the first input of counter 6, a control signal is issued to record the start address code to counter 6, In addition, the signal received at the second input of block 9, through the third element AND 21 and the element OR 27 switches the trigger 23, as a result

At the same time, from its output through the fifth output of block 9, the first input of switch 5 receives a control action, according to which the group of outputs of switch 5 is connected through its

5 nepBjno group of inputs with a group of outputs of counter 6; Changing in the process of counting binary counter code 6 through the group of outputs of switch 5. enters the second group of inputs

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second, comparison circuit 8. When reaching the equality of the code of the counter 6 to the code of the address of the end of the program section (the code of the start address is always no more than the code of the address of the end of the program section), the corresponding signal is generated at the output of the comparison circuit 8. This signal through the third input of block 9, through the third element 1, firmware 26 again sets on the counter 6 the code of the address of the beginning of the program section, after which the counting continues, etc. Thus, on display unit 2, a control curve is displayed corresponding to the technical state of the device. A reference curve corresponding to the good technical support of the device must be obtained on a known good device and may be stored as a control oscillogram in the device's instruction manual. The monitoring process is interrupted by pressing the switch 17.

In the program control mode, the switch 18 is pressed, and from the third 15 and fourth 16 switches, via the third and fourth outputs of block 9, control signals are fed to the first inputs of switches 3 and 4, respectively. In this case, the output group of the switch 3 is connected to its second group of inputs, and the output group of the switch 4 is connected to its second group of inputs. By pressing the switch with the 17 clock pulses arriving at the first input of the block 9 through the first element 22 and 22, the trigger 23 is reset. The control signal from its output through the fifth output of block 9 is fed to the first input of switch 5, connecting its group of outputs with the second group of inputs. The position of all other keys in this mode is irrelevant. In the course of program execution, the codes of its address line corresponding to the course go to the second input group of switch 4, then through the output group of switch 4, through the second input group of switch 5 and through its output group, through the second input group of switch 3 and its output group to a group of inputs of the digital-analogue converter 1. In this case, on the display unit 2, the figure corresponding to the real

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the progress of cyclic program sections.

The dp mappings of the non-cyclic program sections of the device are used as follows. Through the third and quarter outputs of the block 9, the control signals formed by the switches 15 and 16 are fed to the first inputs of the switches 3 and 4. At the same time, the switch 3 is set to its position. the first group of inputs is associated with its group of outputs, and the switch 4 is when its second group of inputs. is associated with its group of outputs.

The initial state of the switch 5 corresponds to the position when its group of outputs is associated with its second group of inputs. The fifth switch 18 is pressed. On the first and second fields of the switches 13 and 14, the working binary codes of the addresses of the beginning and end of the program area being monitored (controlled) are dialed, respectively. At the same time, the Address Address Code from the first dialer of the switch 13 through the first group of outputs of block 9 goes to the group of inputs of the counter 6 and to the first groups of inputs of the first, comparison circuit 7 and switch 4. The code of the address of the end from the second dialed floor of switches 13 through the second group of outputs block 9 is fed to the first group of inputs of the second circuit 8 of the comparison.

By pressing the first switch 17, the device returns to its initial state. In this case, the element AND 22 opens and the sync pulses through the first output of the block 9 are passed to the second input of the counter 6 and to the corresponding inputs of the flip-flops 24 and 23.

5: Press the second switch 19 to start the device. In this case, the sync pulses through the sixth output of block 9 are fed to the first inputs of the first 7, second 8 and third 11 comparison circuits.

When implementing the analyzed program section on the device input group, address codes will be generated sequentially in time

5 corresponding to the beginning and end of this section. The code of the address of the beginning of the analyzed program area through the w-RH group of inputs of the switch 4, through its group of outputs, through the w-5

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rui group of inputs of the collider 5, through its group of outputs enters the second group of inputs of the first comparison circuit 7. As a result, the output of the comparison circuit 7 generates a signal that arrives at the second input of block 9, the third element OR 26 and the seventh output block 9 writes the code of the address of the beginning of the program area to the counter 6, and then through the delay element 28, the second element OR 25 and the second output of the block 9 adds one to the counter 6, and the next expected code a is set on the counter 6 Resa real computational process.

If the computational process fails and the code of the expected address is not pocketed at the input of the device, then the address code set on the counter 6 exactly corresponds to it will be displayed in block 12.

If, however, the expected address code does not occur at the input of the device — and, therefore, at the second group of inputs of the third comparison circuit 11, then the corresponding signal Jr5 is output at the output of the comparison circuit 11 and is fed to the fourth input of block 9. the third input of the second element OR 25, through the second output of block 9 and through the third input of counter 6 provides an addition to the counter code of one more unit, thus forming the code of the next expected address code of the computational process on it, etc. The addition of units to the program can be analyzed.

at counter 6, it continues until the computational process reaches the address code of the end of the program section.

The binary code changed as a result of counting through the output group of counter B goes to the first input group of the first switch 3 and then through its output group to the input group of the digital-to-analog converter 1. The result of the conversion is displayed on the display unit 2. Then the address code of the end of the analyzed program area through the second group of inputs of the switch 4, through its group of outputs, through the second group of inputs of the switch 5, through its group of outputs goes to the second group of inputs of the second circuit 8

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similarly accurate to one command. The control process — the course of the program portion is interrupted by pressing the first switch 17,

Claims (2)

Invention Formula 1, A device for displaying a computational process comprising a digital-to-analog converter and a first indication block, the first and second information inputs of the display unit being connected to the corresponding outputs of a digital-analogue transformer / diverter in order to expand the functionality of the device by providing display of non-repeating or rarely repeating As a result, the output of the comparison circuit 8 produces a signal arriving at the third input of block 9, as a result of which the counter of the beginning of the program section is set again on the counter 6 through its input group and the counting continues. According to the signal received on the third 0 input of block 9 through the scheme OR 27, trigger 23 is switched. As a result, from its output, through the fifth output of block 9, the first input of switch 5 receives the controlling action by which the group of output outputs of switch 5 is connected through its first group of inputs to the output group of counter 6. Changing during counting binary counter code 6 0 through the output group of the switch 5 enters the second group of inputs of the second comparison circuit 8. Upon reaching the equality of the code of the counter 6 to the code of the address of the end of the program section, a corresponding signal is generated at the output of the comparison circuit 8. This signal arrives at the second input of counter 6, resulting in counter 6 again. an address code is set 0 starts the program section and continues counting. Thus, on display unit 2, a working curve is displayed corresponding to the analyzed section of the program and confirming its execution. By iterating through the codes using the first and second dialed fields of the switches 13 and 14, the section 35 five 0 five similarly accurate to one command. The control process — the course of the program portion is interrupted by pressing the first switch 17, Invention Formula 1, A device for displaying a computational process, comprising a digital-analogue converter and a first indication block, the first and second information inputs of the display unit being connected to the corresponding outputs of a digital-analogue transmitter / diverter, in order to extend the functionality devices by providing display of non-repeating or rarely repeating program sections, the device additionally contains three switches, three comparison circuits, a counter, a clock pulse generator, a second display unit, a control unit, the output group of the first KOMNryTaTopa connected to the information input groups of the second display unit and the digital-invertor converter, the first information input groups of the first switch and. the first comparison circuit is connected to the output group of the second switch, the first and second groups of information inputs of which are connected to the output groups of the counter and the third switch, respectively, the first group of outputs of the control unit is connected to the second group of information inputs of the first comparison circuit, with the group of inputs specifying the initial code of the counter and the first group of information inputs of the third switch, the second group of information inputs of which are the group of information inputs of the device control unit is connected to the first group of information inputs of the second comparison circuit, the second group of information inputs of which is connected to the group the outputs of the second switch, the group of outputs of the counter is connected to the second group of information inputs of the first switch AND the first group of information inputs of the third comparison circuit, the second group whose information inputs are connected to the group of outputs of the third switch, the outputs of the first to seventh control unit are connected to the installation input zero of the counter, the counting input of the counter, the control inputs of the first, third and second commutators, the enabling inputs of the first comparison circuit and the counter, in the start, the resolution enable input of the initial address code of the analyzed section, the input of the comparison sign of the initial and final addresses of the analyzed section, the sign of the absence of a fault in the analyzed section of the control unit are connected respectively to the output of the clock generator, equality outputs of the first, second and third comparison circuits whose permissive entries are merged. 2. The device according to claim 1, 1 and 2, is that the control unit contains five switches, two groups of switches, three AND elements, three OR elements, two triggers, a delay element, and a break contact of the first switch connected with the first input of the first element And, the second input of which is combined with the first input of the second element And, the closing contact of the second switch and connected to the start input of the block, the output of the first element I is connected to the zero inputs of the first and second triggers and is the first output of the block, the single inputs of the first and second triggers are combined and connected to the output of the first element 1-SHI, the first input of which is connected to the output of the third element I, the first input of which is combined with the first the input of the third element HJHi and the input of the delay element and is connected to the input of the permission to issue the code of the initial address of the analyzed section of the block; the output: the second element I is connected to the first input of the second element HJHis the second input of which is connected to the output of the delay element, the third input and the output of the second SHS element are respectively the input of the sign of absence in the analyzed section and the second output of the block, the second inputs of the first and third elements OR are combined and connected to the input of the attribute of the comparison of the initial and final addresses of the block, the direct the outputs of the first and second flip-flops are connected respectively to the second input of the second element AND and the fifth output of the block, the disconnecting contact of the second switch and the output of the third element OR connected respectively to the switch and the seventh output of the block, the disconnecting contacts of the third, fourth, fifth switches are connected respectively to the third the fourth outputs of the block and the second input of the third element I, the groups of disconnecting contacts of the first and second groups of switches form the first and second groups of outputs of the block ka, shorts; the contacts of the two groups of switches, the first, third, fourth and fifth switches are combined and connected to the power supply bus of the unit. ..