SU1357950A1 - Device for reducing argument - Google Patents

Abstract

The invention relates to digital computing and can be used to create specialized, information processing systems. The aim of the invention is to increase the speed of the device. The device for bringing the arguments contains the registers of argument 1 and commands 2, multiplexer 3, the elements OR 4, 5, modulo-2 adders 6, 7, the elements AND 8-13 with the corresponding links. This device allows, using the formulas for converting angles to the first quarter of a circle, to calculate the functions sinx, cos X, tan X and ctg X for any angles. 1 dw., 2 tab. has co with joint venture

Description

The invention relates to computing and may find application in the creation of specialized information processing systems.

The aim of the invention is to improve the speed,

In the device, actions are performed on numbers with a comma fixed before the high-order code in the reverse code. For definiteness, we will further assume that the results of the proposed device will be used to implement the functions sin (x), cos (x), tg (x), ctg (x) in the presence of blocks calculating functions

sin (| - Z) and tg (zp, where Z is the modulus of the reduced argument for the functions sin (x), cos (x) to the first quarter of the circle, Zj is the modulus of the reduced argument for the functions tg (x) to one-eighth of the circle.

The representation of the argument X in the reverse code is known to be written with the following expression:

X

X, at X 7/0. l + Cl-Z -lxl), with k: 0,

(one)

where n

the number of bits of the mantissa number.

The expression (1-2 -lxf) of formula (1) corresponds to the formulas of a favorable angle in parts of a circle, obtained by dropping in the formula (3) the two most significant bits x, x Zj - the angle in parts of a circle, obtained by dropping in the formula (1) the three highest bits j Z, Zj, are the inverse values of the ratio of negative angles to positive angles in parts of a circle. Therefore, in the future, the sign of the argument will not be taken into account, and formula (1) will be:

(2)

formula (1) will be:

X X, with X 7 / О + ()., With X 0.

Thus, only positive angles X 6 0.1, represented in parts of a circle, are involved in further transformations.

Positive angles for the device are

. + x 2 + ... + x „2

1 - n

(3)

where is x

2

 - first most significant bit of argument

X2 second senior arggument

Xj is the third highest bit of the argument;

Xf, is the low-order bit of the argument.

In accordance with the known formulas in table. 1 shows the dependences of the modules of the arguments of the Corresponding functions reduced to the corresponding part of the circle, as well as the values of their sign and the calculated function depending on the combinations of the arguments X, X, Xj,

Table 1

55

replacements in each category of units by zero, and zero by units.

The plus sign is encoded with the digit O, and the minus is 1. The sign (. If the functions tg x and w 1 is calculated, if the function ctg is calculated).

In accordance with the table. 1 for the sin function, the value of the reduced argument to the first quarter is calculated by the formula

Z D) if X2 1,

and her sign is Zn,

for the cos function, the value of the th argument is computed

Z 1 2

if x2 1 i if

and her z.nak equal

Zn cos X, © -X-,

where the plus sign means modulo two,

for the function tg, the value of the reduced argument to one-eighth of the circle is calculated by the formula

 2e, 1 zj,

uh, if Xj 0;

if X

The sign U) is calculated by the formula

J vy Aj, and the sign corresponding

Kn t, with t, x,

The drawing shows a device diagram.

The device for bringing the arguments contains the register of 1 argument, the register of 2 commands, multiplexer 3, the elements OR 4 and 5, the adders 6 and 7 modulo two, and the elements AND 8-13, higher bits 14-16 of the argument register, outputs bits 17-19 of the code of the command register, the output 20 of the sign of the calculated function of the device, the output 21 characters of the calculated function of the device, the output 22 of the given device argument.

The device works as follows.

At the input of the register 2 commands gives-, with the command code. The codes on the register of 2 commands, depending on the respective function, are given in Table. 2 (K - first exit, 17; Kj - second exit 18, Kj - third exit 19 of the register of 2 commands).

(four)

sin

(five)

ten

cos

(6)

15

tg

20

The input of register 1 of arguments is given the argument code x in accordance with formula (3), where x, is the first output 14, Xj is the second output 15, x is the third output 15 of the register of arguments. At the output of the second adder 7 modulo two (the first output .20 of the device) signals appear,

PS

 whose function

w X, © X, (10)

 Ij i / j

At the output of the first element OR 5 (the second output of the 21 device), there appears a signal sign of the corresponding function, the logical function of which is equal to

(9)

 , (x, @ x,) + Kz Xj

(eleven)

35 The signal from the output of the second element OR 4 equal to

(12)

, Xj + Kj Xj + KjXg

arrives at the control input of 1 1 multi-40 plexer 3.

At the output of the multiplexer 3 (the third output of the device 22), the code of the given argument is formed in accordance with the formula

if if

1 Z,

(13)

where Z is the direct code from the information register of 1 register of arguments, and Z is the inverse one.

The values of the reduced argument Z, Z to the first quarter are 55 of the value of Z by dropping two of the higher bits, and the value of the reduced argument Z to one-eighth of the circle is formed from Z by scaling three preceding bits.

Claims (1)

Invention Formula A device for providing arguments, containing the argument register, two OR elements, six AND elements, the command register, the outputs from the first to the third most significant bits of the argument register, are connected to the first inputs from the first to the third elements, respectively, characterized in that, In order to improve speed, two modulo-two adders and a multiplexer are entered into it, the first output of the command register is connected to the second input of the first element And the first input of the fourth element And, the second output of the command register is connected to the first inputs of said fifth and sixth AND gates, the third instruction register output connected to second inputs of the second and third AND gates, the outputs of the third, fourth and sixth AND gates are connected to the inputs of said first OR gate, you are a 0 Q 5 the course of which is connected to the control input of the multiplexer, the outputs of the first and third high-order bits of the argument register are connected to the first inputs of the first and second modulo-two adders, respectively, the output of the second high-order register of the argument is connected to the second inputs of the first and second modulators two, the output of the first modulo-two adder is connected to the second input of the fifth element AND, high, first, second, fifth elements AND connected to the inputs of the second OR element, the output of the argum bits The device is connected to the information inputs of the multiplexer, the output of which is the output of the device argument, the outputs of the second modulo-2 adder and the second OR element are the outputs of the calculated function, and the sign of the calculated function of the device.