GB1040241A - Improvements relating to parallel digital adders - Google Patents
Improvements relating to parallel digital addersInfo
- Publication number
- GB1040241A GB1040241A GB1542762A GB1542762A GB1040241A GB 1040241 A GB1040241 A GB 1040241A GB 1542762 A GB1542762 A GB 1542762A GB 1542762 A GB1542762 A GB 1542762A GB 1040241 A GB1040241 A GB 1040241A
- Authority
- GB
- United Kingdom
- Prior art keywords
- carry
- group
- output
- last stage
- inputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
Abstract
1,040,241. Parallel binary adders. ELECTRIC & MUSICAL INDUSTRIES Ltd. April 24, 1963 [April 26, 1962], No. 15427/62. Heading G4A. A parallel binary adder using carry propagation is built up from adder units, each containing a pulse regenerator for a carry signal generated in or propagated by the unit, and the units are divided into a number of groups with separate paths for transmission of carry signals through the group as a whole, and through the individual units of a group, the choice of a regenerated or an unregenerated carry signal for the inputs to a group being made on the basis of the number of units through which an unregenerated carry signal can pass without excessive deterioration. Fig. 2 shows a full adder " building block" having addend and augend inputs H, J, two carry inputs A, B, a " conditional carry " output E, two inputs F, G utilized only in the last stage of a group, sum output K, carry output C and regenerated carry output D. Control signals L, M order addition and subtraction respectively. Fig. 1 (not shown), shows a parallel adder for 20-bit numbers built from the blocks of Fig. 2; the connecting lines in Fig. 1 correspond to those (A-G) crossing the broken line of Fig. 2. A carry is transmitted out of a group such as S4-6 if either (a) a carry input is supplied to input G of the last stage, from the previous group, and conditional carries (from gates 9) are generated by each stage of the group (the diodes 14 of each stage form an AND gate at the F input of the last stage), (b) the last stage generates an " unconditional " carry (gate 8), or (c), the last stage produces a conditional carry signal and receives a carry at its input A which may have been generated within the group or derived from the previous group (in which case a carry output will also be transmitted out of the group according to (a) above). The regenerated carry signal is always used for producing the sum output of the next stage, and regenerators 16 produce an inverted signal for application to gates 13 and 15 for this purpose.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1542762A GB1040241A (en) | 1962-04-24 | 1962-04-24 | Improvements relating to parallel digital adders |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1542762A GB1040241A (en) | 1962-04-24 | 1962-04-24 | Improvements relating to parallel digital adders |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1040241A true GB1040241A (en) | 1966-08-24 |
Family
ID=10058937
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB1542762A Expired GB1040241A (en) | 1962-04-24 | 1962-04-24 | Improvements relating to parallel digital adders |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB1040241A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2184579A (en) * | 1985-12-20 | 1987-06-24 | Texas Instruments Ltd | A multi-stage parallel binary adder |
-
1962
- 1962-04-24 GB GB1542762A patent/GB1040241A/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2184579A (en) * | 1985-12-20 | 1987-06-24 | Texas Instruments Ltd | A multi-stage parallel binary adder |
| GB2184579B (en) * | 1985-12-20 | 1989-10-25 | Texas Instruments Ltd | A multi-stage parallel binary adder |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| GB1522045A (en) | Digital arithmetic units | |
| US3465133A (en) | Carry or borrow system for arithmetic computations | |
| GB1390385A (en) | Variable length arithmetic unit | |
| ES465443A1 (en) | High speed binary and binary coded decimal adder | |
| US3202806A (en) | Digital parallel function generator | |
| GB1040241A (en) | Improvements relating to parallel digital adders | |
| US3697735A (en) | High-speed parallel binary adder | |
| US4704701A (en) | Conditional carry adder for a multibit digital computer | |
| GB1145676A (en) | High speed adder circuit | |
| GB981296A (en) | Improvements in or relating to digital registers | |
| JPS57147754A (en) | Digital parallel adder | |
| GB1171266A (en) | Arithmetic and Logic Circuits, e.g. for use in Computing | |
| GB1203730A (en) | Binary arithmetic unit | |
| JPS5447539A (en) | Digital binary multiplier circuit | |
| US3786490A (en) | Reversible 2{40 s complement to sign-magnitude converter | |
| SU769538A1 (en) | Device for adding numbers in redundant binary notation | |
| US3548182A (en) | Full adder utilizing nor gates | |
| JPS6450123A (en) | Adding device | |
| SU932479A1 (en) | Pulse distributor | |
| SU1357950A1 (en) | Device for reducing argument | |
| SU582512A1 (en) | Device for raising to the third power | |
| GB1033155A (en) | Improvements relating to circuits for the transmission of digital code signals | |
| SU1531090A1 (en) | Multiple-input parallel adder | |
| SU974588A1 (en) | Threshold logic element | |
| SU842789A1 (en) | Microprocessor section |