SU1356213A1 - Discrete matched filter - Google Patents

Abstract

The invention relates to radio engineering and m. used to filter pseudo-random signals under interference conditions. The purpose of the invention is to improve the accuracy of filtration. The discrete matched filter (DPF) contains adder 1, the first group of n signal processing channels 2-1, ...,: 2-p, generator 3 pseudo-random code, frequency divider 5, generator 6 clock pulses. To achieve the goal, a code converter (PC) 4 and a second group of n signal processing channels are introduced, identical to the signal processing channels of the first group. The code at the output of PC 4 is the time inverted sequence with which the DPF is matched. Because the output code of PC 4 is present only in N samples, where N is the number of elements of a pseudo-random sequence (psi), then the remaining samples will only give noise in the DPF response. On the day of elimination of this deficiency, the signals of both outputs of PC 4 repeat it; input chipboard, and in the absence of a code the level of the first output corresponds to the level of the logical unit, and the second output - the logical zero T This ensures mutual interference compensation. 2 Il. WITH

Description

1135

The invention relates to radio engineering and can be used to filter pseudo-random signals under interference conditions.

The purpose of the invention is to improve the accuracy of the fusion.

Figure 1 shows an electrical block diagram of a discrete matched filter; 2 shows timing diagrams for his work.

Discrete matched filter (figure 1) contains the adder 1, the first. a group of n signal processing channels 2-1, ..., 2-p, a generator of 3 pseudo-service code, a converter of 4 codes, a frequency divider 5, a generator of 6 clock pulses, a second group of n signal processing channels 7-1, ..., 7-p

Each of the signal processing channels of the first and second groups 2-1, ..., 2-n and 7-1, ..., 7-n contains the register 8 of the code, the buffer register 9, the analog storage unit 10 and the shift register 11.

The discrete filter works as follows.

Elements of the input signal (Fig. 2a) using a register 11 controlled by

a clock pulse generator 6 and a frequency divider 5 are sequentially recorded in the cells of the analog storage unit 10.

The register 11 records the pulse from the output of the frequency divider 5 (Fig. 26), and the pulse propagation through the register provides a generator of 6 clock pulses. The pseudo-random code generator 3 generates a pseudo-random sequence of discrete signals (Fig. 2b), which is inserted into the code registers 8 through code converter 4. The code at the output of converter 4 is the time inverted sequence with which the matching matched filter is matched. To ensure signal delay invariance, the length of the processing channel must be 2T, i.e. the number of cells of the analog storage unit 10 is equal to, where N is the number of elements of a pseudo-random sequence; m is the number of memory cells in the buffer register 9. Since the output code of converter 4 (Fig. 2d) is present only in K samples (in the interval 0-Tj), the remaining samples will be given in the discrete response

-

d

g

five

0

0

five

0

13 2

matched filter only noises. To eliminate this drawback, the signals of both outputs of converter 4 repeat its input pseudo-random sequence in the code following interval, and in the absence of code the level of the first output corresponds to level 1, and the second output - to level O (fig.2g, d). This ensures the mutual compensation of interference, which is provided by samples that interact in the absence of a code. Through a buffer register 9 controlled by a clock pulse generator 6, the contents of each register cell 8 of the code are multiplied with the contents of the corresponding cell of the analog storage unit 10 and the received signals are added up in adder 1, thus forming the response of a discrete matched filter (Fig. 2e). At the moment of coincidence of the signal elements with the elements of the reference code, the main response is observed at the output of the adder 1, at other points in time — side emissions of the autocorrelation functions of the signal.

Claims (1)

Invention Formula Discrete matched filter containing serially connected clock pulse generator and pseudo-random code generator, frequency divider whose input is connected to the clock pulse output, and output connected to another input of the pseudo-random code generator, adder, whose output is the output of the filter, as well as the first group from n signal processing channels, each of which contains serially connected code register, buffer register and analog storage unit, the second input of which is The signal input of the signal processing channel of the first group and the shift register, the first outputs of which are connected to the third inputs of the analog storage unit, the output of which is the signal output of the signal processing channel of the first group, while the clock inputs of the code register, buffer register and shift register are combined and are the clock input of the signal processing channel of the first group connected to the output 313 the clock generator, the signal input and output of the code register are the input and output of the reference code of the signal processing channel of the first group, and the signal input and output of the shift register are the input and output of the signal scan signal processing channel of the first group, the signal inputs which are combined and are the input of the filter, the input of the scan signal of the first channel of processing the signal of the first group is connected to the output of the frequency divider, and the inputs of the reference code and the scan signal ix are The signal processing signals of the first group (, n) are connected respectively to the outputs of the reference code and the scanning signal of the previous processing channels of the signal of the first group, characterized in that, in order to improve filtering accuracy, a code converter and a second group of n processing channels are entered into it signal, identical to the signal processing channels of the first group, with the first 1П п ГППП п ГППП п п UUU LJ rcUuLJ LJ / 7 (UUU II zgs shp ppp shshd 13-4 the input of the code converter is connected to the output of the pseudo-random code generator, the second input is connected to the output of the frequency divider, the first output is connected to the input of the reference code of the first channel of the first group signal processing, and the second output is connected to the input of the reference code of the first channel of the second group signal processing signal input scanning of which is connected to the output of a frequency divider, while the clock inputs of the signal processing channels of the second group are combined and connected to the output of the clock generator, the signal outputs of the processing channels b the second group of signals is connected to the inputs of the adder, the inputs of the reference code and scan signal ix of the signal channels of the second group (, n) are connected respectively to the outputs of the reference code and scan signal of the preceding signal processing channels of the second group, and the signal inputs of the signal channels of the second group are combined and connected to the input of the filter. hts y- FIG. 2