SU1347082A1 - Signature analyzer - Google Patents

Abstract

The invention relates to computing and can be used in test equipment of discrete objects. The purpose of the invention is to increase the speed of the device. The signature analyzer contains information inputs 1, clock input 2, trigger 3, elements 4, 5, the first group of shift registers 6, the second group of shift registers 7, the switch group 8, and the group of adders 9 modulo two. The signature analyzer can be used to monitor binary sequences that have a frequency. the accompanying pulses are twice the maximum frequency of switching the shift registers. 1 il. sl o hk S.K 1.K -8.1 1.1 o I a / f / V 5 / 9.K - / / .5 / с 4 О 00 N5

Description

The invention relates to computing and can be used in test equipment of discrete objects.

The purpose of the invention is to increase the speed of the device.

The drawing shows a diagram of the signature analyzer.

The signature analyzer contains information inputs 1, clock input 2, trigger 3, elements 4 and 5, shift registers 6 and 7 of the first and second groups, respectively, switch group 8 and adder group 9 modulo two.

The device works as follows.

In the binary sequence generator mode, before starting operation, the shift registers are set to one of the allowed states. The type of the generated sequence is determined by the type of control actions received at the inputs 1, which are connected either to the log busses. 1 and O, or to the corresponding

These are the outputs of trigger 3. In this mode, the outputs of the device are the outputs of modulo-two adders, from which shifted copies of binary sequences are taken, and their frequency is twice as high as the switching frequency of the shift registers. The total size of the shift registers is determined by the degree of the generating polynomial. When working in a signature analysis mode, before starting operation, all shift registers are set to the zero state. The reset circuits are not shown.

The last bits of the registers of the first and second groups alternately perform the functions of the last bits of the shift registers of the known device. Depending on the clock number, each switch connects the outputs of the corresponding shift registers either to the i-ro input or to the (i + 1) -ro input of modulo two.

When using the device in the mode of generating binary sequences at the outputs of modulo-two adders, copies of the binary sequence are shifted by more than one clock cycle, while

The device trigger 3 can be used to increase the period of the generated sequence.

Claims (1)

Invention Formula A signature analyzer containing the first group of k shift registers (where k is the number of information inputs of the analyzer) and a group of k modulo-two adders whose outputs are connected to informational the inputs of the corresponding shift registers of the first group, the groups of bit outputs of which are the first group of outputs of the analyzer, whose information inputs are connected to the first inputs of modulators are two groups, differing in that, in order to increase speed, the analyzer additionally contains a second group of k registers shift, a group of k switches, two elements And a trigger, the counting input of which is connected to the first inputs of elements And is the clock input of the analyzer, the second group of outputs of which is formed by groups of different outputs of shift registers of the second group, information inputs of which are connected to the outputs of the corresponding adders modulo two groups, the second and third inputs of the ix modulo adders are connected respectively to the second outputs of the (i-1) -x switches and the first outputs of the ix switches, where, k, the second and third inputs are first About the modulo adder two are connected respectively to the second output of the k-ro switch and the first output of the first switch, the first and second information inputs jx of the switches are connected respectively to the outputs of the last bits jx of the first and second groups of shift registers (where j 1, k) are controlled the input inputs of the switches are combined and connected to the second input of the first element AND and connected to the forward output of the trigger, the inverse output of which is connected to the second input of the second element AND, the outputs of the first and second elements AND are connected respectively venno with clock inputs of the registers ADD-yoke of the first and second groups.