SU1343408A2 - Modulo two summer - Google Patents

Abstract

The invention relates to computing and can be used in pulse logic circuits for various purposes. The purpose of the invention is to increase the reliability of the adder. The input signals are fed to the inputs of the second 8 and third 9 differentiation nodes, the positive signals from the outputs of which are received respectively at the inputs of the second 10 and third 11 pulse shapers. The signals from the outputs of the formers 10 and 11 pulses are received respectively at the first and second inputs of the elements OR-NOT 1 and AND-NOT 2. At the output of the element OR-NOT 1, a pulse is formed, the duration of which is equal to the logical sum of the durations of the input signals, at the output of the element AND -ON 2 a signal is generated whose duration is equal to the logical product of the duration of the input signals. The signal from the output of the element OR NOT 1 through the first node 5 of the differentiation enters the third input of the element 6, the output of which through the first driver 7 of pulses is connected to the output of the adder. The output element AND-NOT 2 through the expander 3 pulses connected to the second input element And 6 and the input element 4 delay, the output of which is connected to the first input element And 6. 2 Il. with tS (L 00 CO N O 00

Description

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The invention relates to computing technology, can be used in pulsed logic circuits for various purposes and owes to the improvement of the device according to the author. No. 1117633.

The purpose of the invention is to increase the reliability of the operation of the adder.

Figure 1 shows the functional diagram of the adder, - figure 2 is a time diagram of the operation of the adder.

Modulo two contains the elements of the IPI-NOT 1 and AND-NOT 2, the expander 3 pulses, the element 4 delay,

the first differentiation unit 5, the element 65 and the first pulse shaper 7, the second 8 and the third 9 differentiation nodes, the second 10 and the third 11 pulse shapers.

Modulo two works as follows.

The input pulse sequences arrive at the second 8 and third differentiation nodes 9, differentiate themselves with their front (start the drivers for 10 and 11 pulses with fonts. From the outputs of the drivers for 10 and 11 pulses of the sequence of pulses arrive at the element OR NOT 1. The duration of the signal coming from the output of the element OR NOT 1 to the input of the first node 5 of differentiation is equal to the total duration of the information

mapping signals d and e. Forbidding 35 is responsible for the first and second inputs

Signal 3, arriving 1-5Y from the output of the element AND-NOT 2 to the input of the expander 3 pulses, has the duration of the coinciding parts of the information signals.

Due to the delayed signal, passing through the delay element 4 to the first input of the element 6, the signal j;

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passing to the third input element And 6, eliminated the false signals caused by the mismatch of the front and leading edges of the information. signals. The expander 3 pulses and the element 4 delay built in such a way that the total duration of the signals from their outputs is equal to the sum of the maximum durations of the input information signals. The output of the element 6 is connected to the input of the first pulse shaper 7, the output of which is the output of the adder.

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From the timing diagram (Fig. 2) it can be seen that reliable operation of the proposed adder is maintained when the input signals are not matched in time by an amount equal to the duration of the input signal, and when the lawsuit is reached; 1 x of signal durations by almost any value.

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Modulo two by aut. St. 1117633, characterized by:

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operation, the second and third differentiation nodes are introduced into it, the second and third pulse formers, and the inputs of the second and third differentiation nodes are respectively

the adder, the outputs of the second and third differentiation nodes are connected to the inputs of the second and third forms, respectively: a) pulse generators, the outputs of the second and third pulse formers are connected respectively to the first and second inputs of the OR-NOT and NAND elements.

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Claims (1)

Claim The adder modulo two by author. St. 'ft 1117633, characterized in that, in order to increase the reliability of the work, the second and third differentiation units, the second and third pulse shapers are introduced into it, the inputs of the second and third differentiation nodes being the first and second inputs of the adder, the outputs of the second and third nodes, respectively differentiation are connected to the inputs of the second and third pulse shapers, respectively, the outputs of the second and third pulse shapers are connected respectively to the first and second inputs of the elements OR-NOT and I-N E. gp I — 1 ΓΊ --1__1— | _G “ Ί 1—1 ____ 1 and. to -G ~ “1_g and ~ - - -Ί to_ 1_ / \ —D r ~ ί __________________: _____