SU1336102A1 - Storage unit - Google Patents

Abstract

The invention relates to computing and can be used in the exchange of information in multiprocessor computing systems. The purpose of the invention is to increase the reliability of the device. The storage device contains the write address registers 1, drives 4, write number registers 5, address registers 7, read address decoders 9, AND-OR elements 10, read number registers 11, control block 13, comparison blocks 19, first 20 and second 21 groups elements AND, conflict resolution blocks 22, element OR-NOT 23, element OR 25, and group of elements OR-NOT 27. The device detects errors when simultaneously writing numbers from several directions to the same address, detecting and eliminating incorrect chi reading sat down while simultaneously reading and reading information at the same address. 1 h. n. f-ly, 3 ill. i (L with so C5 fus. I

Description

The invention relates to computing and can be used in the exchange of information in multiprocessor computing systems.

The purpose of the invention is to increase the reliability of the device.

FIG. 1 shows a block diagram of a storage device; in fig. 2 is a block diagram of the conflict resolution block; in fig. 3 - storage drive structure.

The storage device (Fig. 1) contains the registers 1 write addresses, the information inputs of which are the address inputs 2 of the device record, the decoders 3 write addresses, the accumulators 4, the registers 5 the record number, the information inputs of which are the information inputs 6 of the device, the registers 7 addresses read information inputs of which are address read inputs 8, read address decoders 9, AND - OR 10 elements, read number registers 11, whose outputs are device information outputs 12, control unit 13 laziness inputs recording and reading resolution which are respectively 14 inputs recording and reading device 15. The control unit contains blocks 16-18 delay.

The device also contains comparison units 19, the first 20 and second 21 groups of AND elements, conflict resolution blocks 22, the OR element NO 23, the output of which is the device ready output 24, the OR element 25, the output of which is the device output 26, and group of elements OR NOT 27.

Each collision resolution block 22 (Fig. 2) contains comparison blocks 28, AND elements 29, OR element 30, AND-OR element 31 and delay element 32.

Each accumulator 4 (Fig. 3 contains an AND-OR 33 element, a memory cell 34 and an OR element 35.

The storage device is multi-way and is intended for online exchange between subscribers and for storing system arrays and tables in multiprocessor computing systems.

Information is recorded in the device as follows. The source subscribers, via inputs 2, send address codes to inputs of registers 1, and number codes to inputs 6, to inputs of registers 5. These codes are accompanied by corresponding recording signals from block 13. In addition, recording signals go to inputs of conflict resolution blocks 22 to determine conflicts when simultaneously writing and reading at the same address and at the corresponding inputs of the And 20 elements. In blocks 19, a pairwise comparison is made of each with each write address. If simultaneously recording signals from i-ro and j-ro subscribers are sent to the same address, then at ij-th block 19 a coincidence signal is generated, which is fed to the ij-th element AND 20 and then to the ij-e inputs i-ro and j-ro elements OR-NOT 27, the outputs of which block on the iM and JM elements AND 21 signals from the i-ro and j-ro outputs of the elements 16 delay on

 control of the baffle 3. In addition, from the i-ro and j-ro elements AND 20, the signals arrive at the element OR 25, the output of which is the output 26 of the device. If there is no simultaneous recording from several directions to the same address, then the elements OR NOT 27 allow the signals from the outputs of the control unit 13 to pass to the control inputs of the decipherors 3. The signals from the outputs of the selected outputs of the decoders 3 are supplied to the inputs accumulators 4, which control the passage of a number through the element AND-OR 33 from the outputs of the registers to the numerical input of the memory cell 34, and through the element OR 35 set the recording mode in it.

The information is read as follows.

The receiving subscribers pass through the inputs 8 to the inputs of the registers 7. These codes are accompanied by the corresponding read signals from the block 13. The read signals through the delay blocks 17 are fed to the inputs of the conflict resolution block 22, in which the blocks 28 are compared one read address from register outputs 7, with all write addresses. When the read and write addresses coincide and simultaneously access the drives 4 by writing and reading one of the AND 29 elements, a signal is sent that, through the OR 30 element, switches the AND-OR 31 element so that its output read signal for Vits detained for one cycle of access to the drive 4.

In addition, signals from the outputs of the element OR 30 are fed to the element OR-NO 23, the output of which is the readiness output 24 of the memory device. When a conflict is detected, the readiness output 24 is set to a low level that prohibits circulation from

Q subscribers-sources for one cycle of access to the drive 4.

Thus, in a conflict situation, the write access in drive 4 passes without delay, and the read access and resolution of calls from source sources is delayed by one call cycle to drive 4. The output of the AND-OR element 31 will open the corresponding decoder 9. Signals from the outputs

decoder 9 is fed to the inputs of memory cells 34, in which information is read controlled, which through the corresponding AND-OR 10 element controlled by the output of the decoder 9 is fed to the inputs of the corresponding registers 11. At this time, the read signals from the output of delay blocks 17 delay blocks 18 control the writing of the read information to the corresponding registers 11. Next, the read information is fed to the output 12 of the memory device. If the read and write addresses do not match, then the read signal passes without a delay to the output of the collision resolution unit 22, and the memory ready signal will remain at the ready output 24. The signal from the output of block 22 conflict resolution is fed to the input of the corresponding decipher 9 and further, similarly to the previous case.

Claims (2)

1. A storage device containing write address registers, write address decoders, record number registers, drives, control unit, read address registers, read address decoders read number registers and AND-OR elements, and the information inputs of the write address registers are write address inputs the device, the outputs of the write address registers are connected to the information inputs of the corresponding decoders of the write address, the outputs of which are connected to the write sampling inputs of the corresponding drives, The memory inputs of the write number registers are information inputs of the device, the outputs of the record number registers are connected to the information inputs of the respective accumulators, the information inputs of the read address registers are the address write inputs of the device, the outputs of the read address registers are connected to the information inputs of the corresponding read address decoders whose outputs are connected to the read sample inputs of the respective memory drives and the first inputs of the AND-OR elements whose outputs are connected to the information inputs of the read number registers whose outputs are the information outputs of the device, the second inputs of the AND-OR elements are connected to the information outputs of the respective accumulators, the write enable inputs of the control unit are the write inputs of the device, the read enable inputs of the control unit are read inputs devices, the outputs of the first group of the control unit are connected to the control inputs of the number registers records and write address registers, the outputs of the second group of the control unit are connected to the control inputs of the read number registers, the outputs of the third group of the control unit are connected to the control inputs of the read address registers, which are different in order to increase the reliability of the device comparison blocks, first and second groups Q elements AND, group of elements OR-NOT, element OR, conflict resolution blocks, element OR-NOT, with the inputs of the comparison blocks connected to the corresponding outputs of the write address registers, the outputs of the comparison blocks 5 are connected to the first inputs of the AND elements of the first group, the second and third inputs of which, the first inputs of the AND elements of the second group and the control inputs of the conflict resolution blocks are connected to the corresponding outputs of the fourth group of the control unit, the first outputs of the conflict resolution blocks are connected to the element inputs OR NOT, the output of which is the device readiness output, the outputs of the elements AND of the first group are connected to 5 inputs of the OR element and with the inputs of the corresponding OR-NOT elements, the outputs of which are connected to the control inputs of the write address decoder, the address inputs of the recording of conflict resolution blocks are connected to the outputs of the address registers 0 entries, address inputs of the readout of conflict resolution blocks are connected to the outputs of the read address registers, synchronization inputs of the conflict resolution blocks are connected to the outputs of the fifth group of the control unit, the second outputs of the conflict resolution blocks are connected to the control inputs of the read address decoders, the output of the OR is output device failure. 2. The device according to claim 1, characterized in that each conflict resolution block contains comparison blocks, AND elements, OR element, delay element and AND-OR element, wherein the outputs of the comparison blocks are connected to the first inputs of the AND elements whose outputs are connected to the inputs of the OR element, the output of which is connected to the first and second inputs of the AND-OR element and is the first output of the block, the output of the AND-OR element is the second output of the block, the output of the delay element is connected to the third input of the AND-OR element, the input of the delay element fourth entrance to the ele the AND-OR and the second inputs of the AND elements are combined and are the control input of the block, the first inputs of the comparison blocks are the address input of the block record, the second The 5 inputs of the comparison units are the address read input of the block, the third inputs of the AND elements are the clock input of the block. 0 Figg Phage. J Compiled by V. Rudakov Tehred I. VeresKorrektor G. Reshetnik Circulation 589 Subscription VNIIPI USSR State Committee for Inventions and Discoveries 113035, Moscow, Zh-35, Raushsk nab. 4/5 Production and printing company, Uzhgorod, ul. Project, 4 Editor A. Kozoriz Order 3809/49