SU1332523A2 - Generator of uniformly-distributed pseudorandom quantities - Google Patents

Abstract

The invention relates to a pulse technique and is an additional invention to auth.St. No. 1202038 The purpose of the invention is to enhance the functionality. To achieve the goal, a block of 16 memory registers, a block of 18 multiplier groups, a block of 17 groups of AND elements, a group of 20 delay elements and a group of 19 OR elements are entered into a generator of uniformly distributed pseudo-random variables. The generator also contains 1.3 trigger pulse generators, delay elements 12, 7, 13, OR 4, trigger 5, 6 clock pulses, counter 8, AND group 9, block 10 of memory registers, 11 block of groups of AND elements, group of 12 elements EXCLUSIVE OR, comparison unit 14, memory register 15. This generator allows the formation of interdependent coordinates of a pseudo-random two-dimensional vector. 1 il. C (L from 00 ISD ate to from

Description

The invention relates to a pulse technique and is an improvement of the invention on an avtoSV. No. 1202038.

The aim of the invention is to enhance the functionality of a generator of uniformly distributed pseudo-random variables by forming the coordinates of a pseudo-random two-dimensional vector.

The drawing shows a block diagram of a generator of uniformly distributed pseudo-random variables.

The generator of uniformly distributed pseudo-random variables contains the first generator 1 trigger pulses, the first delay element 2, the second generator 3 trigger pulses, the element OR 4, the trigger 5, the generator 6 clock pulses, the second delay element 7, the counter 8, a group of 9 elements And, the first block 10 memory registers, the first block of 11 groups of elements AND, a group of 12 elements EXCLUSIVE OR, the third element 13 of delay, comparison block 14, register 15 of memory, the second block 16 of memory registers, the second block of 17 groups of elements AND, block 18 groups of multiplier group of 19 elements OR, group of 20 elements of delay about

The output of the generator 1 trigger pulses is connected to the installation inputs of the first 10 and second 16 blocks of memory registers, the installation input of the counter 8, the installation input of the memory register 15 and through the first delay element 2 with the first input of the trigger 5, the output of which

first generator 1 triggering pulses. The outputs of elements And groups of 9 elements And are connected with the first inputs of elements And corresponding

groups of the first block 1I groups of elements And and through the corresponding delay elements of a group of 20 delay elements with the first inputs of elements

10 And the corresponding groups of the second block 17 groups of elements And, the second input of the elements And groups of elements And which are connected to the corresponding outputs of the second block 16 registers

15 memories. The outputs of the elements of the first block and 11 groups of elements and are connected to the corresponding inputs of the group of 12 elements EXCLUSIVE 1-SHI through the first inputs of the elements OR of group 19

20 OR elements, the second inputs of the OR elements of which are connected to the corresponding outputs of the block 18 groups of multipliers, the first inputs of the corresponding multipliers of which are connected to

25 corresponding outputs of the corresponding registers of the first block of 10 memory registers, and the second inputs of the corresponding groups of multipliers with the corresponding outputs of the elements

30 corresponding groups of the second block 17 groups of elements And

The generator of uniformly distributed pseudorandom variables works as follows.

35 When the device is turned on, the control voltage is applied to the generators 1 and 3 of the triggering pulses. In this case, the generator of the 3 triggering pulses produces a pulse, which

connected to the input of the generator 6 clock-40 through the element OR 4 sets in the out of pulses, the output of which is the zero state trigger 5. After

one with the synchronization input of the counter 6 and through the second delay element 7 with the first inputs of the corresponding elements AND of the group 9 of the elements AND, the second inputs of the elements AND of which are connected to the corresponding outputs of the counter 8 and the corresponding inputs of the first group of inputs of the comparison unit 14, the second group of inputs of which are connected to the corresponding outputs of the memory register 15. The output of the comparator unit 14 is connected to the second input of the trigger 5 via the third delay element 13 and the first input of the OR 4 element, the second input of which is connected to the output in the second generator 3 trigger pulses, the input of which is connected to the input of the first generator 1 trigger pulses. The outputs of the elements And a group of 9 elements And connected with the first inputs of the elements And the corresponding

groups of the first block 1I groups of elements And and through the corresponding delay elements of a group of 20 delay elements with the first inputs of elements

And the corresponding groups of the second block are 17 groups of elements And, the second inputs of the elements And groups of elements And which are connected to the corresponding outputs of the second block 16 registers

memory The outputs of the elements of the first block and 11 groups of elements and are connected to the corresponding inputs of the group of 12 elements EXCLUSIVE 1-SHI through the first inputs of the elements OR of group 19

the OR elements, the second inputs of the OR elements of which are connected to the corresponding outputs of the block 18 groups of multipliers, the first inputs of the corresponding multipliers of which are connected to

the corresponding outputs of the corresponding registers of the first block of 10 memory registers, and the second inputs of the corresponding groups of multipliers with the corresponding outputs of the AND elements

the corresponding groups of the second block are 17 groups of elements AND,

The generator of uniformly distributed pseudorandom variables works as follows.

When the device is turned on, the control voltage is applied to the generators 1 and 3 of the triggering pulses. In this case, the generator of the 3 triggering pulses produces a pulse

delay time transients in the trigger 5 generator 1 trigger pulses produces a pulse

which sets in the zero state the counter 8 and to the corresponding state triggers of the first 10 and second 16 blocks of memory registers and register 15 of memory. In this case, in memory register 15, the number τ is set corresponding to the number of points to be formed by the device, which is ensured by a corresponding output connection of the generator 1 trigger pulses to the inputs of the trigger 15 of the memory register 15. In the registers of the first block, 10 ami registers are set: in the first register the number V, 2, in the second

V, 2, etc. up to V, T 2, In the regn register of block 16 of memory registers are set: in the first register number G | 1, in the second Tj 3 in the third g 7, in the fourth g 15, etc. The setting of the numbers in the registers of blocks 10 and 16 of the memory registers is done in the same way as the installation of triggers in the register 15 of the memory. In addition, the pulse from the output of the generator 1 trigger pulses after a delay in the element 2 of the delay for the transient time in the memory register 15, the first 10 and second Ih memory register blocks arrive at the first input of the trigger 5 and sets it to one. As a result of this, the clock pulse generator 6 starts to work, the first pulse from the output of which counter 8 goes into the state corresponding to the number of the first point, the coordinates of which should be recorded by the device. The pulse from the generator output is 6 clock pulses after the delay element 7 delays the transient time in counter 8 to the inputs of elements AND of group 9 of elements I, from the outputs of which signals corresponding to the discharge of bits of counter 8 are fed to the inputs of the corresponding groups of block 11 groups of elements AND, which ensures the passage of codes of the corresponding registers of the block of 10 memory registers to the outputs of the block of 11 groups of elements AND IN the elements EXCLUSIVE OR groups of 12 elements EXCLUSIVE OR, which receive codes from you odov sides groups I1 of the AND, manufactured addition signals applied to their inputs. As a result, at the outputs of the device, a sequence of values of the first coordinates of the points are formed, the numbers of which are sequentially formed by the counter 8.

The signals from the outputs of a group of 9 elements And also come through the delay elements of a group of 20 delay elements and the inputs of groups of elements AND of the block 17 groups of elements I, which ensures that the codes of the corresponding registers of block 16 of memory registers pass to the outputs of the block 17 of groups of elements I. These codes are multiplied into block 18 groups of multipliers with corresponding codes of registers of block 10 of memory registers. Results ne

0

five

0 25

The multiplications are added to the EXCLUSIVE OR elements of the 12 elements of the EXTENDING WITNING elements with the signals from the outputs of the block of 11 groups of AND elements, as a result of which the sequence of the second coordinates of the points, the numbers of which are sequentially generated by the counter 8, are formed at the device outputs. clock pulses at the outputs of the device, pairs of numbers are formed corresponding to the coordinates of the next point of the two-dimensional space. The formation process continues until the code at the outputs of the counter 8 becomes equal to the register register 15 of the memory, after which the comparison unit 1A generates a pulse, which through the third delay element 13 and the OR element 4 sets the trigger 5 to the zero state, which causes to stop the generator 6 clock pulses about

Claims (1)

Claims of the Invention Generator of evenly distributed pseudorandom variables according to the authors. No. 1202038, characterized by the fact that, in order to extend the functionality by forming the coordinates of the pseudorandom-} of the first two-dimensional vector, the second block of memory registers, the block of groups of multipliers, the second block of groups of elements I, the group of elements are additionally introduced into it delays and a group of elements OR, outputs of elements AND of a group of elements AND, through corresponding singing elements of a delay, groups of delay elements are connected to the first inputs of elements AND of the corresponding groups of the second block of groups of elements And, the second inputs of elements And groups elements And which are connected to the corresponding outputs of the second block of memory registers, the installation input of which is connected to the output of the first generator of trigger pulses, the outputs of the elements AND of the first block of groups of elements AND are connected to the corresponding inputs of the group of elements EXCLUSIVE WRIT the inputs of the elements OR of the group of elements OR, the second inputs of the elements OR of which are connected to the corresponding outputs of the block of groups of multipliers, the first inputs of the corresponding groups cleverly 1332523 ° the inhabitants of which are connected to the corresponding groups of multipliers — with the corresponding outputs of the corresponding outputs of the elements AND of the corresponding registers of the first block of registers of the corresponding groups of the second block of memory groups, and the second inputs of the corresponding AND elements,