SU1328941A1 - Code synchronization device - Google Patents

Abstract

Invention m. used in digital transmission systems with multi-level signals. The purpose of the invention is to increase the retention time and reduce the recovery time. The device contains a code pulse identifier, a counter-drive and a decision block. The principle of operation of the device is shown in FIG. 3. In FIG. For given a binary signal, on the silt. The ST is a four-level signal (HOS). In case of an error-free transmission of the HOS, the Chep irichesk SinK / 1Y JI iyu and with the correct determination of the boundaries of code groups (kg), the values of the digital sum (CS) at the boundaries of the CG correspond to those shown in FIG. Sound If, when receiving an HOS, in the result of an error, the symbol 3 is taken instead of 2, then the CA on the CG boundary will exceed the limit value +2 and will be equal to +4 (Fig. G). If, instead of symbol 2, symbol 1 is received, the CA on the CG border will exceed the limit value of -2 and will be equal to -4 (Fig. Aft). The case of incorrect CG boundaries is shown in FIG. Ze. The values of the CA at the boundaries of the CG are shown in FIG. Zh The probability of exceeding the limiting values of the CS when the CG boundaries are incorrectly determined is greater than 1/6. The device is intended for operation in digital information transmission systems with the code ЗВ20 over radio frequency modulated circuits. 2 tab., 2 3. p. F-ly, 3 ill. § (L: eo: about 4;

Description

1328941

refers to electric ti chi am pr yes va

and can be used in digital transmission systems with multi-level signals.

The purpose of the invention is to increase the retention time and reduce the recovery time.

FIG. I presents the structural electrical circuit of the code synchronization device; in fig. 2 - timing diagrams for the operation of the device; in fig. 3 - the principle of operation of the device.

The device code synchronization 2 5 sings from the table. I, transmitted by four

The reich signal has a limited digital C5TPMA at the coding boundaries of groups with extreme values of +2 and -2, and this device detects digital sum values at the boundaries of code groups that exceed the specified extreme values of +2 k

and decisive block 3, where the identifier 1 of the code pulses consists of blocks 4 and 5 of the separation of code pulses, the inverter 6, the distributor of 7 pulses, blocks 8 and 9 of the shift and the IL 10 element, and blocks of the distribution of 4 and 5 code pulses identical in the form of sequential -2.

Register 11 (12), parallel to re- The principle of operation of the device code slot 13 (14), the counter 15 (16) of digital synchronization is shown in FIG. 3. a large sum in the code group, a digital sum counter 17 (18) on the border of the code groups, a memory block 19 (20) and a code pulse shaping block 21 (22), and the drive count 2 consists of ND flip-flops 23-26 .

The code synchronization device operates as follows.

The conversion of three binary symbols (3B) to two quarter-length (2Q) on the transmission side occurs in accordance with the table. i.

thirty

35

FIG. An embodiment of the binary signal is shown, and FIG. 3b is a four-level signal obtained from this binary signal in accordance with the closed transform shown in Table. I In the case of an error-free transmission of a four-level signal and the correct determination of the code group boundaries, the values of the digital sum at the boundaries of the code groups will correspond to those shown in FIG. Sound If during the reception of a four-level signal (Fig. 3b), as a result of the display, for example, symbol 3 is received instead of symbol 2 (arrow in FIG. 36), then after several time intervals the digital sum at the code group boundary will exceed the limit value +2 and equals +4 (fig. 3g). Similarly, if instead of symbol 2, symbol 1 is received, then the digital sum at the boundary of code groups will exceed the limit value -2 and will be equal to -4 (Fig. A). The frequency of exceeding the boundary values of a digital sum with correct determination of the boundaries of code groups is proportional to the error rate Pp. To ensure control (–p. Of exceeding the limit values of the digital sum, it is necessary to restore the nearest limit value of the digital sum after each excess (Fig. 3g, g).

Table 1

B tab. 1 next to each quaternary code group, a digital value is specified in this group, calculated as the algebraic sum of the amplitudes of the pulses in the code group, provided that the characters 0,1,2,3 of the code are assigned a normalized voltage of -3, -1, , +3.

Over each of the three columns of code groups in the table. 1 indicates the value of the digital sum at the boundary of the code groups at the time the next binary group enters the encoder. How barely

The reich signal has a limited digital C5TPMA at the coding boundaries of groups with extreme values of +2 and -2, and this device detects digital sum values at the boundaries of code groups that exceed the specified extreme values of +2 k

-2

The principle of operation of the code synchronization device is shown in FIG. 3

FIG. An embodiment of a binary signal is shown, and FIG. 3b is a four-level signal obtained from this binary signal in accordance with the fixed conversion shown in Table 2. I In the case of an error-free transmission of a four-level signal and the correct determination of the code group boundaries, the values of the digital sum at the boundaries of the code groups will correspond to those shown in FIG. Sound If during the reception of a four-level signal (Fig. 3b), as a result of the display, for example, symbol 3 is received instead of symbol 2 (arrow in FIG. 36), then after several time intervals the digital sum at the code group boundary will exceed the limit value +2 and equals +4 (fig. 3g). Similarly, if instead of symbol 2, symbol 1 is received, then the digital sum at the border of code groups will exceed the limit value -2 and will be equal to -4 (Fig. A). The frequency of exceeding the boundary values of a digital sum with correct determination of the boundaries of code groups is proportional to the error rate Pp. In order to ensure that the limits of the digital sum exceed the limits, it is necessary to restore the nearest limit of the digital sum after each exceed (Fig. 3g, g).

3

The case of incorrect determination of code group boundaries for the same four-level signal is depicted in FIG. Ze. The values of the digital sum at the boundaries of the code groups in this case are presented in Fig. Zh Moreover, the probability of exceeding the limit values of the digital sum with incorrect determination of the boundaries of code groups is greater than 1/6.

Differences in the probabilities of exceeding the limit values of the digital sum with the correct and incorrect determination of the boundaries of code groups are the basis for constructing a code-synchronization device in a digital transmission system with code ЗВ2Й.

The code synchronization device is intended for operation in digital information transmission systems with a code over radio frequency modulated circuits. - When a frequency-modulated signal is received at the correlation detector of quadrature components, two binary signals, и and,, are formed at its outputs, representing the quaternary symbols 0,1,2,3 in the Gre code (Fig. 3 h, ii).

The binary digital signals y and y of the pulse boundary of which are shown in FIG. 2a are fed to the input pins, respectively, and are written to the successive registers 11 and 12 by a clock signal from the output of the inverter 6 (Fig. 2c). The boundaries of the first and second pulses (Fig. Z, 3) Z and Z in the code group are located on the first and second outputs of the first serial register 11 and the first and second pulses Zj and Z (fig. Z) on the first and second outputs of the second serial register 12 (Fig. 2d, d). Distributor 7 pulses, which for the 3B2U code is a divider. with 2 direct and inverse outputs, it generates two pulse sequences (Fig. 2e, g), one of which is a code sync signal.

Consider the process of entering into synchronicism, i.e. process, drive w; s to coincidence of the positive pulse front in the code sync signal (Fig. 2e) with the beginning of the first pulse in the code group (Fig. 2a).

The first Z, Z and second Z, Z pulses (Fig. 2d, d) of binary signals Y are written to parallel register 13 by a signal from the first

ten

15

28941

the output of the distributor 7 pulses (Fig. 2e), and in the parallel register 14, the signal from the second output of the distributor 7 (Fig. 2g). The signals from the outputs of the parallel registers 13 and 14 are fed to the inputs of the I5 and 16 digital sums in the code group respectively, and in the counter 15 the digital sum of the second pulse in this code group and the first pulse in the next one is counted, and in C4et4mce 16 is the digital sum of pulses in code group.

The algorithm for calculating the digital sum of two adjacent pulses is presented in Table. 2

Table 2

From the outputs of counters 15 and 16 digital sums in the code group, the values of the digital sums, presented in binary form, are received respectively at the inputs of counters 17 and 18 of the digital 513.

where they add up to the previous value of the digital sum in the code group, which is not in binary form, from the first and second outputs of the memory blocks 19 and 20.

The new value of the digital sum at the boundary of the code groups is recorded in blocks 19 and 20 of memory with signals from the outputs of blocks 8 and 9 of the shift (Fig, 23, l), respectively. The signal boundaries at the outputs of memory blocks 19 and 20 are shown in FIG. 2 and m

Excess limit values (-2 and +2) of the digital sum, fixed in counter 17, appear with a probability greater than 1/6, and in counter 18, with a probability proportional to the failure rate of the GROCH, the digital sum values exceeding +2 appear at the third output, and exceeding the value of -2 at the fourth output of memory blocks 19 and 20. Pulse drivers 21 and 22 generate narrow pulses at the moments when the limit values of the digital sum are exceeded (fig. 2k, n), which set the nearest values of the digital sum at the output of memory blocks 19 and 20, and which are combined in the ORIO element (fig, 2o) and arrive at the clock inputs of the D-flip-flops 23-26 of the accumulator counter 2, At the informational input, the D-flip-flop 23 receives a signal from the first output of the distributor 7 pulses (FIG. 2e), and the pulses (FIG. 2K), with probability P, u 1/6 at the outputs of block 21 for forming code pulses, write zeros (fig, 2e) in the D-flip-flops 23-26 of the counter-drive 2, Once in. all D-flip-flops 23-26 will be written down the zeros at the output of the decision block, a pulse is formed (fig. 2 p), rephasing the pulse distributor 7 (fig. 2e, g) and thereby setting the true phase value of the code sync signal to it. The same impulse (fig, 2 p) is set

In the successive state, the D-triggers 25 and 26 of the counter-accumulator 2.

Claims (1)

1. Code synchronization device containing series-connected identifier of code name5 O f5 0 0 5 0 five pulses, the clock and clock inputs of which are, respectively, device inputs, a counter-drive and a deciding unit, characterized in that, in order to increase the retention time and reduce the synchronization recovery time, the output of the decision block is connected to the set-up inputs of the counter-accumulator and code pulse detector, whose half-pulse pulses are output from the device, 2, The device according to claim 1, 1 and 2, so that the identifier of the code pulses consists of two parallel-connected 1 x allocation blocks of code pulses, each of which consists of a series-connected serial register, a parallel register, the inputs of which are respectively combined with the inputs of the parallel register of the second block for allocating code pulses and connected respectively to the serial code conversion, in parallel with the outputs of the serial registers of these blocks, a digital counter th sum in the code group, a digital sum counter on the border of the code group, a memory block, two of the outputs of which are respectively connected to two installation inputs of a digital sum counter on the border of code groups, and a code generation unit, two outputs of which are connected to the installation inputs of the block memory and through the OR element combined with the outputs of the second. the code extraction unit and the output of the code identification code pulse, the signal input of which is the serial register of each code extraction block, and the clock input are inputs of the parallel-connected inverter, the output of which is connected to the downstream input of the serial register of each code allocation block pulses and one of the inputs of the first and second blocks of shift, and the pulse distributor, the inverse and direct outputs of which are respectively connected Eny with recording inputs of parallel registers of the second and first blocks of the separation of code pulses and the second inputs of the first and second blocks of shift, the outputs of which correspond to 113289418 but connected to the recording inputs, 3, The device according to claim 1, 1, about the first and second memory blocks in the first and second blocks, so that the counter — such as the allocation of code pulses — with the accumulator is made of this direct output and the setup input of the connected N D-flip-flops, the pulse distributors are the co-inputs of which are combined, and Responsible is the output of half-pulses and the installation input of the code pulser. the last L D-flip-flops, the setup inputs are combined and are the setup input of a drive counter. IGC T I 2 I /  T / T i 2   I