SU1327172A1 - Apparatus for detecting digital magnetic record playback signals keyed by frequency and phase - Google Patents

Abstract

This invention relates to the accumulation of information. The purpose of the invention is to reduce the error of the detection result by reducing the effect of phase modulation of the marker features. The information input of the memory block 38 is received from the switch output 35 bits of information with replaced information symbols, the first address input is the code of write addresses from the output of counter 23, the second is the code of write addresses from the output of commentator 36, the sync input is pulses from the output multivibrator 21. Memory unit 38 delays information. The pulses of the multivibrator 21 in the marker zone record the difference code calculated by subtracting unit 37 into the cells of memory block 38, whose addresses are given by code from register output 34. Counter 24 output code sets addresses of memory block 38, from which the difference code is read by synchro pulses trigger 29. A bus 40 receives information bits in which there is no error. Sync pulses go to bus 39, and marker pulses to bus 41 — 1 SP.

Description

 one

The invention relates to the accumulation of information, namely, devices for detecting mannulated signals in frequency and phase of a digital magnetic recording reproduction signal.

The aim of the invention is to reduce the error of the detection result by reducing the effect of phase modulation of the marker features. The drawing shows f5. nktsional-- on the device diagram

A device for detecting frequency and phase reproduction signals of a digital magnetic recording sabl {it is playback unit 1, pkgococheyyny through the formatter 2 pulses on the extremum of mothers to the first inputs of the first element And 3 and the first trigger 4 and through 5 pulses on the levels to the second inputs of the first element I 3 and the first trigger 4 connected by the output to the first input of the second trigger 6 connected by the second input to the output of the decoder 7, the Last is connected by the input through the first counter 8 pulse s with the output of the generator 9 pulses. The second trigger 6 is connected by a second input to the first inputs of the first, second and third counting triggers 10, 11 and 12 and the third and fourth trigger 13 and 14 connected to each other and connected to the first input of the second element I 15 connected to the second trigger by the second input 13 connected by the second input to the output of the second counting trigger I l, the third input with the interconnected output of the first element I 3, the second input of the second counting trigger 11, the control input of the first counting trigger 10 and the first input the third its element And 16 connected by a second input to the interconnected output of the first counting trigger 10 and the first input of the fourth element And 17. The fourth element And 17 is connected to the second input of the second element And 15, the second input of the third counting trigger 12, connected to the output with the second input of the fourth trigger 14, and the first input of the fifth element And 18 connected by the second input to the output of the fourth trigger 14 and

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output to the second input of the first counting trigger 10,

In addition, a device for detecting the manipulated; The frequency and phase of the digital magnetic recording playback signals contain the first, second and third multivibrators 19, 20 and 21, the sixth element And 22, the second and third counters -23 and 24 pulses, the delay element 25, the fifth, sixth, seventh and eighth triggers 26-29, the first and second shift registers 30 and 31, the first and second elements OR 32 and 33, the parallel register 34J, the first and xx switches 35 and 36, the subtraction unit 37 and the memory unit 38, the first waiting for the multivibrator 19 connected by the input to the output of the first counting trigger 10 and the output to the first inputs n trigger 26 connected by a second input to the output of the third element AND 16, sixth trigger 27 connected by a second input to the output of the seventh trigger 28 connected by a second input to the output of the fourth ment And 17, the first shift register 30 connected to the second input the output of the fifth trigger 26, the second shift register 31 connected by the second input to the output of the sixth trigger 27, the second counter 23 B-Shul-CoBj connected by the second input to the output of the sixth element I 22, the eighth trigger 29, the parallel register 34, Perv waiting multiview The selector is also connected to the output of the first of the output buses 39 and the input of the second standby multivibrator 20 connected by output to the first input of the sixth element I. connected to each other. 22 connected by the second input to the first output of the second shift register 31, the second element OR 33 and the input a delay element 25 connected by an output to interconnected a second input of a second element OR 33, connected by an output through a third standby multivibrator 21 to a first input of memory block 38, and to a first input of second switch 36, connected .the second input with the output of the first element OR 32, the third input through the third counter 24 pulses with the first output of the second counter 23 pulses and with the second input of the parallel register 34, the fourth input with the output of the parallel 13 of the 13th register 34 and with the first input of the subtractor 37, connected to the second input with the output of the third counter 24 pulses. The second switch 36 is connected by an output to a second input of a memory unit 38 connected by a third input to a second output of a second pulse counter 23 by an output to a second input of an eighth trigger 29 connected by an output to a second output, bus 40 and fourth input to the output of the first switch 35, connected by the first input to the output of block 37, the second input to the output of the first shift register 30, the third input to the output of the sixth trigger 27 and the first input of the first element OR 32 and the fourth input to the second output of the second register 31 a, the second input of the first element OR 32, the third input of the parallel register 34 and the third output bus 41.

The proposed device works as follows.

The playback unit 1 performs the playback, amplification and filtering of the signal containing the markers, in the following period of which the information about the meaning of the two information symbols in the marker is enclosed.

3; The shapers of 2 and 5 pulses form pulse sequences according to the extrema and the levels of the reproduced signal. The clock signal from the output of the first counting trigger 10 is fed to the input of the multivibrator 19, which generates the clock pulses corresponding to the signal drop of the same name. The impulses of information 1 from the output of the element 16 set a high potential at the output of the trigger 26, which retains a high potential at the output until the sync pulse from the output of the multivibrator 19 sets a low potential at the output of the trigger 26. The signal from the output of the trigger 26 each the sync pulse is stored on the first and delayed on the second section of the first shift register 30. As a result, at the output of the shift register 30, digits of digital information are formed, corresponding to the information O and 1, synchronous with the clock pulses from the output of the multivibrator 19. Marker pulses from the output of the AND 17 element

. set high potential on

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trigger output 28. Trigger 28 maintains a high potential at the output until the first clock pulse from the output of the multivibrator 19 sets a low potential at the output of the trigger 28, which is remembered for each sync Rosh-Shulv on trigger 27. As a result, at the output of the trigger 27 form and marker pulses

. one-bit information synchronized with sync pulses. The pulses of the markers for each clock pulse are delayed twice by the second shift register 31.

At the same time, for each sync pulse, the multivibrator 20 generates gating pulses that arrive at one of the inputs of element AND 22. At the other input of element And 22, there are delayed pulses from the second output of the second shift register 31. At the moment of coincidence of these pulses, the pulses are formed at the output of the element 22 and which set the pulse counter 23 to the zero state. The counter 23 pulses counting clock pulses forms larallelnsh. the code of the address of the entry arriving at the address input of the memory unit 38. A pulse counter 23 also controls a third counter 24 pulses, the capacity of which

 is equal to 4. A pulse counter 24 generates a parallel two-digit code, which at the moment it arrives at the control input of the parallel register 34 of the delayed marker pulse from the output of the shift register 31 is stored by the sync pulse in the parallel register 34. , to another input of which a code from the output of the counter of 24 pulses is received, As a result, from the output of the subtractor 37, a parallel two-digit code, which, depending on the period of the markers, receives the value 00, 01, Yu, 11, arrives at one information input of the first switch 35, Switch 35 at the moment the marker pulses from the outputs of flip-flop 27 and the second shift register 31 arrive at its control inputs, replacing information received at its other information input from the first register 30 shift, two information characters in the head. „

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value of the value 00, 01, 10, 11 of the code at the output of the block 37 of the calculation.

At the same time, parallel two-digit codes from the outputs of the counting of 24 pulses and register 34 are fed to nn (}). The secondary inputs of the second switch 36. One control input of the switch 36 from the output of the first electrical element OR 32 receives a pulse generated as a result of the summation of pulses. markers from the trigger trigger 27 and the second output of the second shift register 31. The other control input of the switch 36 receives strobe pulses from the output of the multivibrator 20, delayed by delay element 25 (its parameters are chosen such that the pulses from its output do not overlap in duration with the pulses of the multivibrator 20), when there is no switch on the first control input 36 pulses from the output of the element I.PI 32 to the second address input of the memory block 38 through the switch 36 connects the output of the register 34. If there are 36 pulses from the output of the element OR 32 at the first control input of the switch, 1 shpulsa output from the delay element 25, 36 to the second address input unit 33 PAG-STI 36 is connected through the switch 24 the pulse counter output "

 .

Simultaneously on. element OR 33

the pulses from the outputs of the multivibrator 20 and the delay element 25 are added, which are then fed to the input of the multivibrator 21, which forms short pulses located inside the pulses from the output of the element OR 33

 Thus, the II format input of the memory unit 38 comes from switch 35; information bits are replaced with information symbols; the first address input is the address write address code from the counter 23, and the second address input is the address address code from the switch 36 output. , to the synchronizing input - pulses from the output of the multivibrator 21, the Memory unit 38 carries out the information delay. The emulsifiers of multivibrator 21 in the marker zone are used to write the difference code calculated by subtractor 37 into the cells of memory 38, whose addresses are

0

five

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5 0 -5

five

0

50 .

0

72 .6

are given by a code from register output 34, by a code from output of counter 24, the addresses of the cells of memory block 38 are set, from which the synchro-shuhls read the difference code to the eighth trigger 29, as a result, information 40 is received on head 40 which does not contain an error caused by modulation the period following marker features. Synchro pulses fall on the bus 39 post, and 41 marker pulses fall on the bus.

Claims (1)

Formula of gain A device for detecting manipulated; in the frequency and phase of the playback signals of a digital magnetic recording, comprising a playback unit connected by an output through a pulse shaper by extremes to the first inputs of the first element And of the first trigger and through a pulse shaper by levels to the second inputs of the first element And the first trigger connected by the output to the first input of the second trigger connected by the second input to the output of the decoder connected by the input through the first counter of pulses the output of the pulse generator, and to the interconnected first inputs of the first, second and third counting triggers and the third and fourth triggers and connected output to the first input of the second element I, - connected to the second input with the output of the third trigger connected to the second input to the output of the second counting trigger , the third input with interconnected output of the first element And, the second input of the second counting trigger, the control input of the first, pulse counter and the first input of the third element And, connected The second input to the connected - between itself the output of the first counting trigger and the first input of the fourth element I, connected by the second input to the output of the second element And, second, the third input of the third counting trigger, connected to the second input of the fourth trigger, and the first entrance n to-. And, connected by the second input to the output of the fourth trigger and output to the second input of the first counting trigger, and output buses, characterized in that, in order to reduce the error of the detection result due to the reduction of the phase modulation of the marker features, It introduced the first, second and third pending multivibrators, the sixth And element, the second and third pulse counters, the delay element, the fifth, sixth seventh and eighth-flip-flops, the first and second shift registers, the first and second elements OR, parallel the register, the first and second switches, the subtractor and the memory block, the first waiting multivibrator is connected by an input to the output of the first counting trigger and the output to the first inputs of a fifth trigger connected by a second input to the output of the third element And, the sixth trigger, pa connected the second input to the output of the seventh trigger, the seventh trigger connected by the second input to the output of the fourth element And, the first shift register connected by the second input to the output of the fifth trigger, the second shift register connected by the second ohm with the output of the sixth trigger, the second pulse counter, connected by the second input to the output of the sixth element And, the eighth trigger of the parallel register, and connected to the first output bus and the input of the second waiting multivibrator connected to the output from the interconnected First inputs a hundred element AND connected by the second input to the first output of the second shift register, the second OR element, and to the input of the delay element connected by the output to the second input of the second OR element interconnected output through the third standby multivibrator to the first input of the memory unit, and to the first input of the second switch connected by the second input to the output of the first element OR, the third input through the third pulse counter to the first output of the second pulse counter and to the second input of the parallel register, fourth input with the output of the parallel register and with the first input a subtraction unit connected by a second input with the output of the third. counter IM pulses, and the output connected to the second input of the memory unit connected by the third input to the second output of the second pulse counter, output to the second input of the eighth trigger connected by the output of the second output bus, and the fourth input to the output of the first switch connected to the first input to the output of the subtraction unit, the second input to the output of the first shift register, the third input to the output of the sixth trigger and the first input of the first SH and four inputs to the second output of the second shift register, the second in the course of the first SHS element, the third input of the parallel register and the third output bus. fr- "-" - sa t.J / ....,.-jl. pi-, pj 45 72 t; AT H / 7 75 T go J LH J / four 47 J5 Editor L.Povkhan Compiled by V. Dobrovolsky Tehred L.OlkynykCorrector L.Pilipenko Order 3404/49 Circulation 589 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk iab., d. 4/5 Production and printing company, Uzhgorod, st. Project, 4 HS five -as .: T - 3 T Z-. J7