SU1322304A1 - Device for simulating directional graphs - Google Patents

Abstract

The invention relates to computing and can be used to solve problems of organizational management and graph theory. The purpose of the invention is to increase the reliability of the device due to the control of the presence of contours on the graph. The goal is achieved by the fact that the device contains a control unit, the first and second units of technology formation, a block of branch models, a clock pulse generator. - 3 Il.

Description

And jerking refers to the numerical technique, and can be used to solve problems of organizational control and graph theory.

The purpose of the iso-steroids is to increase the reliability of the device operation by controlling the presence of contours on the graph.

Figure 1 shows a structural device; FIG. 2 is a block diagram of a topology shaping unit; on fig.Z - block diagram of the block model of branches.

The device comprises a control unit 1, a first block 2 forming a flat, a second block 3 forming a topology, a block 4 of branch models, a generator of 5 clock pulses.

The control unit 1 contains the first to fourth memory nodes 6-9, the first and second triggers 10 and 11, the first to the seventh elements OR 12-18, the first to the third delay elements 19-21, the first to the sixth elements AND 22 -27, HE element 28, long path measurement node 29, device graph contour marks input 30i, device graph branches accomplishment input 302, output 31 and 32 numbers of the block 2 and 3 branches being prepared for modeling, outputs 33 and FOR of the search for a free block branch 2 and 3, outputs 35 and 36 of the number of the analyzed branch of blocks 2 and 3, outputs 37 and 38 of the check are completed and the branches of blocks 2 and 3, the outputs 39 and 40 of the interrupt search of blocks 2 and 3.9, outputs 41 and 42 of the number of the loaded node of the graph of blocks 2 and 3 are informational inputs 43-48 of blocks 2 and 3, output 49 of the sign of the result of calculating the longest path of block 2, output 50 of model number of block 4, output 51 of unoccupied branch models, output 52 of interrupt of block 4, information inputs 53-55 of block 4, first and second clock inputs 56 and 57 of block 2, first and second clock inputs 58 and 59 of block 3, information entry

60block 4, first and second outputs

61 and 62 of generator 5, control input 63 of block 1, start 64 of block 2, stroke 65 of the number of the initial branch of the device’s graph, input 66 of start of the block 3, input 67 of the number code of the final branch of the device’s graph, input 68 of reading the numbers of the contour nodes

device graph, output 69 paths contour path on the device graph, you

five

five

0 5

0

The course 70 of the sign ppichin pic.chl device, 71:) the beginning of the longest way to graph.

Blocks 2 and 3 of the topology formation each contain a node 72 of memory numbers of initial nodes of network branches, a node 73 of memory numbers of end nodes of network branches, a node 74 of memory of numbers of output branches of network nodes, a node 75 of memory of numbers of incoming branches of network nodes, node 76 of the memory of the numbers of the first exiting branch of the network nodes, node 77 of the memory of the numbers of the first incoming branch of the network, register

78 outgoing branch number, register

79 branch numbers, end node number 80 register, end network register 81, triggers 82 and 83, decoders 84 and 85, code comparison decoder 86, delay lines 87 and 88, OR elements 89-95, AND 96-101 elements, element NOT 102.

Memory nodes 72-77 are designed to store topology information in the forward network modeling, memory node 72 is used to store the number of the start node of the branch at the address of this branch number, node

73 in memory for storing the number of the end node of a branch at the address of the number of this branch, memory node 76 for storing the number of the first branch from the list of branches leaving the node at the address of the node number, memory node 77 for storing the number of the first from the list branches included in this node at the node number address, node

74 for storage — for storage, in the form of lists, of branch numbers originating from network nodes, memory node 75 — for storage, for lists, for branch numbers entering into network nodes.

Register 78 is intended for intermediate storage of the branch number when identifying branches leaving the node, register 79 for intermediate storage of branch numbers entering the node, register 80 for storing the number of the network node being analyzed, register 81 for permanent storage of the final host.

The state decoders 84 and 85 are designed to compare the codes arriving at them with the code combination X, which is fixed in the scheme, and the code comparison decoder 86 is used for bitwise comparison of the codes from registers 80 and 81.

3132230 4

Each branch model 103 contains a time interval former 104, triggers 105 and 106, elements AND 107-112, element OR 113, and elements 114 and 115 delays.5

The branch model search circuit 116 contains the address encoder 117 and the elements OR 118-120.

The operation of the device is considered by the example of monitoring the presence of circuits in 10 of the calculated network and determining the numbers of network nodes that belong to a closed path.

The device works as follows. five

At nodes 72-77 of the memory of the topology formation unit 2, lists of the modeled network are entered in the form of lists. Registers 78-80 are zeroed in, and register 81 is a drift: it’s the end node number code 20. The triggers 82 and 83 of the topology shaping unit 2 are set to the zero state. In units 72-77 of the memory of block 3 ford from the initial network node, and to the pole 63 of the topology formation unit 3, the code of the branch number is included in the terminal network node.

At some point, the Start signal, which arrives at the pole 64 of the topology formation unit 2, passes through the OR 95 element and sets the trigger 83 to the one state, which allows the passage of a series of pulses from the GS (pole 57) and GI2 (pole 56), respectively, through the AND elements 100 and 101. In addition, the Start signal is fed to the input of delay element 87 and to the read input of the node 72 of the memory of the initial nodes. When a read signal is received at memory node 72, the memory cell is read at the address of the branch number coming from pole 65. Since the branch is selected as leaving the starting node of the simulated network, the output node of memory node 72 appears at the output of memory node 72 which comes through

world topology in the form of lists element OR 90 on the address input of the node

The network topology information is recorded, which is a mirror image of the simulated network, i.e. at memory node 72 at each branch

the number of its end node is recorded, 30 is passed during delay element 87, and

to node 73 of memory at the address of each branch — number of its initial node; to node 74 of memory as lists — numbers of incoming branches; to node 75 of memory as lists — output numbers of branches, to node 76 of memory at address each node is the number of the first incoming branch; in memory node 77, at the address of the number of each node is the number of the first output branch.

Registers 78-81 are zeroed. Triggers 82 and 83 are set to the zero state. Information on the duration of each branch of the simulated network is recorded in the memory node 8 of the control unit 1. Memory node 7 is zeroed. Memory node 6 is labeled with labels for those addresses whose node numbers are in the simulated network. Triggers

The recorded code of the first output branch from the output of the register 78 goes to the address input of the memory node 74, as well as through the output pole 31 of the topology shaping unit 2 and the element OR 12 of the control unit 1 to the address 11 and 10 of the control unit 1, the set input of the node 9 memories and information in the zero state. Triggers on-line input of node 8 of memory of block 1 up105 (1), 103 (2), ..., 105 (p) and 106 (1), 106 (2), .. ,, 106 (n) of block 4 models of branches set to zero.

After the initial setting on the pole 65 of the topology shaping unit 2, the branch number code is issued, then the pulse GI2, shifted relative to the pulse GI1, is fed to the read input of the memory node 74, 55 sampling, at the address of the first branch leaving the starting node, the second branch going out from the same node. Simultaneously, from the initial network node, and to the 63 pole of the topology formation unit 3, the code of the branch number that is included in the terminal network node.

At some point, the Start signal, which arrives at the pole 64 of the topology formation unit 2, passes through the OR 95 element and sets the trigger 83 to the one state, which allows the passage of a series of pulses from the GS (pole 57) and GI2 (pole 56), respectively, through the AND elements 100 and 101. In addition, the Start signal is fed to the input of delay element 87 and to the read input of the node 72 of the memory of the initial nodes. When a read signal is received at memory node 72, the memory cell is read at the address of the branch number coming from pole 65. Since the branch is selected as leaving the starting node of the simulated network, the output node of memory node 72 appears at the output of memory node 72 which comes through

76 of the memory of the first outgoing branch. After a delay time sufficient to read information from the memory node 72, the Start signal appears on

through the element OR 89 to the read input of the memory node 76. This signal is used to read from the memory node 76 the code of the branch number, which is

the first in the list of branches leaving the initial network node. The code of the first output branch from the output of the memory node 76 through the element OR 91 is fed to the information input of the register 78

output branch and is written into it by the first pulse GI1, received at the control input of the register from the output of the element 100.

The recorded code of the first output branch from the output of register 78 goes to the address input of memory node 74, as well as through the output pole 31 of the topology shaping unit 2 and the element OR 12 of the control unit 1 to the address input of memory node 9 and the information input of the node 8 of the memory of control unit 1. Then the pulse GI2, shifted relative to the pulse GI1, is fed to the read input of the memory node 74, sampling, at the address of the first branch leaving the initial node, the number of the second branch leaving the same node. At the same time on them 5132230 /.

pulse GI2 snnl.ch psnp kaodoodnoy model through nodohnoy the field 3} block 2 forming the topology and the element | OR 13 of the control unit 1 is fed to the read input of the memory node 9, to the 5 input of the delay element 20, to the write input of the 6 node of the memory of the control unit 1 and to the input pole 60 of the search for a free model of the 4 branch model blocks. At the same time, the code of the number of the loaded O network node via the output pole 61 of the topology shaping unit 2 and the OR element 16 of the control unit 1 is fed to the address input of the memory node 6. A reading of the length code of the loadable branch of the network from the memory node 9 is carried out. This code, via the output pole 53 of control unit 1, enters unit 4 of branch models.

The search signal for a free branch model from pole 60 is fed to the inputs of the And 109 (1) and 110 (1) elements of the first model 103 (1) branch of the block 4 of the branch models. Since all branch models are free, the trigger 105 (1) is in the zero state and the signal from the output of the element 110 (1) through the element 115 (1) of the delay arrives at the input of setting the single state of the trigger A

With r1OD1 O1oik (Bt THH to the approach, it reads its number from the topology simulation unit 2, reads its duration from the control unit 1 memory of the control unit 1, searches for a 4 mslle branch-free model, writes to the free model time interval generator the code for the duration of the branches

15

the model address of the branch at node 8. In addition, an O is written to the memory node 6 at the starting node address of the load branch.

Further, the code of the number of the next branch arrives from the node 72 of the memory of the outgoing branches of the topology formation unit 2 at the address of the number of the first branch leaving the node through the element OR 91 to the informational

the input of register 78 and with the arrival of the second pulse, the GI1 is written into the indicated register. The code recorded in the register 78 is fed back to the address input of the memory node 74, as well as through pole 31 and the OR element 12 to the address input of the memory node 9 and the information input of the memory node 8 of the control unit 1. With the arrival of the second im25

ra 105 (1). The trigger, through the delay time of the GI 2, from the dimming memory node 9, sufficient for the operation of all of them, is read the duration of the second elements, is set to one, which means that this model is occupied by the modeling process. At the same time, the signal from the output of the 35 Element I 110 arrives at the first input of the I-111 element. and through the element OR 113 to the input of the address coder. At the second input of the element I 111 through the input pole 53, the code for the duration of the branch model branch 40 40 is in unit video. This code is recorded as a state, the search signal of the free source information in the model driver from the output of the element 109 (1) 104 (1) of the time interval. From the output of the address encoder 117, the code of the branch model number through the pole 50 enters the address input of the node 9 of the memory of block 1

a swarm coming from the node of the branch and arrives through the pole 53 to the inputs of the elements I 111 (1), 111 (2), ..., 111 (n) of all the models of the branches of the block 3 of the models of the branches. At the same time through the pole 60 (1) to the inputs of the elements And 109 and 110 receives the search signal of the free model of the branch. Since the trigger 105 (1) first

through pole 60 (2) enters the inputs of the elements And 109 (2) and 110 (2) of the second model of the branch. Since the trigger 105 (2) of this branch model is in the zero state, the signal from the output of the And 110 element is fed to the input of the And 111 element. To the second input of the control. After a time sufficient to organize the described processes, in block 4 models of the branch at the output

The delay element 20 of block 1 of control-50 ment AND 111 receives a duration code; a signal arrives at the input to the recording of node 9 of the memory of the numbers of simulated branches. The number of the loaded network branch is written to the address of the selected branch model. This completes the preparation of the first branch leaving the initial network node for the modeling process.

BUT

With r1OD1 O1oik (Bt THH to the approach, it reads its number from the topology simulation unit 2, reads its duration from the control unit 1 memory of the control unit 1, searches for a 4 mslle branch-free model, writes to the free model time interval generator the code of the duration of the branches, recording the number of the branch of the network

the model address of the branch at node 8. In addition, an O is written to the memory node 6 at the starting node address of the load branch.

Further, the code of the number of the next branch arrives from the node 72 of the memory of the outgoing branches of the topology formation unit 2 at the address of the number of the first branch leaving the node through the OR 91 element to the information

the input of register 78 and with the arrival of the second pulse, the GI1 is written into the indicated register. The code recorded in the register 78 is fed back to the address input of the memory node 74, as well as through pole 31 and the OR element 12 to the address input of the memory node 9 and the information input of the memory node 8 of the control unit 1. With the arrival of the second them

the pulse GI 2 from the node 9 of the memory of lengths is read the duration of the second model of the branch is in the single state, the search signal of the free model from the output of the element AND 109 (1)

a swarm coming from the node of the branch and fed through the pole 53 to the inputs of the elements And 111 (1), 111 (2), ..., 111 (n) of all the models of the branches of the block 3 of the models of the branches. At the same time through the pole 60 (1) to the inputs of the elements And 109 and 110 receives the search signal of the free model of the branch. Since the trigger 105 (1) first

- the pulse GI 2 from the node 9 of the memory of durations is read out the duration of the second -35 40 branch model is in the single state, the search signal of the free model from the output of the element AND 109 (1)

through pole 60 (2) enters the inputs of the elements And 109 (2) and 110 (2) of the second model of the branch. Since the trigger 105 (2) of this branch model is in the zero state, the signal from the output of the And 110 element is fed to the input of the And 111 element. To the second input, the

the branches, which is recorded in the time interval generator 104 (2). At the same time, the signal from the output of the element 110 through the element 115 (2) of the delay sets the trigger 105 (2) to one state. In addition, the signal from the output of the element 110 and through the element OR 113 enters from ml Illll (} lp, rr (p I 17 , 1Л1КЧ Л, Г De fp) miurots code and (1М (|). H of this model is net.) T () G count cg of SO eats nl dresnny phol of node 8 of memory iomeron simulated branches of control block 1. On the arrival of the chapi signal - gi from delay element 20, the network number of the branch is recorded at the address of the branch model number.

The described process of preparing the network branches for modeling continues until the last branch is prepared, leaving the long host. In this case, the X code is read from the address of its memory node 74, KoTopbrfi is written to register 78. The output of register 78 is connected to the state decoder 84, so a signal appears at the output of the latter. This signal goes to zero. Simultaneously sig

trigger input 83, resetting it to the zero state. In addition, the signal from the output of the decoder through the SHSh 92 element enters the pole 39, from which the interrupt search signal through the OR 17 element enters the input of the trigger 11 of the control unit 1, sets it to one state. At the same time, the interrupt search signal is fed to the pole 55 of the branch model block. Since at the moment described (all branches originating from the initial network node are prepared) there are no branch models that have completed the simulation, there will be no interrupt signal from the model block of branches at pole 52, and the trigger 11 of control unit 1 remains in one state.

The unit state of the interrupt trigger 11 permits the passage of the GI2 series pulses through the AND 22 element to the counting input of the long path measuring unit 29 of the control unit 1 and through the pole 54 to the AND 12 (1), 112 (2), ..., 112 elements ( p) all models of branches of the block 4 models of branches. For those models of branches in which the trigger 105 is in the single state, the impulse of the GI2 series arrives at the input of the formers 104 in the time interval. This continues until at least one of the time interval shapers 104 generates a signal that the time modeling process for the duration of the branch has ended.

In PCh1M glc lao git nlly gnogoja form1trpvatelry 104 (1), 104 (2), ..., 104fn) ppeMOHHoin interval tmtupana on single triggers

106 (1), 106 (2) 106 (p), setting them to the helical state. At the same time, the signal from the outputs of the formers 104 (1), 104 (2), ..., 104 (p) comes through the circuit of the scientific research institute 118 to

interrupt search input (1,1) of the first M () delhi branch. In the case that the tri1-ger 106 (1) of the first model of the branch is in the single state, the interrupt signal from the I1 element of the AND 108 (1) enters through the IL11 119 element and the pole 52 into the control unit 1. In addition, the interrupt signal from the output element And 108 (1) is fed to the input of the trigger 105 (1), set it to

five

five

0

five

0

five

The interrupt from the output of the AND element 108 (1) through the ШШ 113 element (1) is fed to the input of the encoder 117, and through the delay element 114 (1) sets the trigger 106 (1) to the zero state. From the encoder 117, the code of the model number of the branch that completed the simulation, via pole 50, is fed to the address input of the node 8, memory numbers of the simulated branches of the control unit 1. The read input of the specified memory node from pole 52 receives an interrupt signal. There is a reading, according to the model number of the branch, the number of the network branch. This code goes to poles 43 and 44, and through the element OR 18 to the address input of the memory node 7. After a time sufficient to read the branch number, a signal arrives at the input of the memory node 7 through delay element 19, and 1 records the completion of the modeling process for this branch at the branch number address. After a time sufficient for recording the mark of accomplishment, the signal from the output of delay element 21 arrives at the first inputs of elements AND 26 and 27. As the flip-flop trigger 24 is currently in the zero state, there is a resolving potential at the second input of element 26 and the start of the analysis of the accomplishment of the branch goes from its output to the pole 47 and further to the unit 2 of the formation of the topology. At the second input of the element And 27 there is a prohibiting potential from a single output

the trigger 10, therefore, the signal to start the analysis of the branch is not received in the topology generation unit 3. This precludes the inclusion of the topology formation unit 3 at the stage of network modeling in the forward direction.

In the topology generation unit 2, the branch number code from the pole 43 arrives at the address input of the final memory node 73, and the start analysis signal of the branch from the pole 47 enters the trigger 82 and sets it to one state. A single trigger state 82 resolves a passer; therefore, in this node

The pulse of the GI1 through element 5 to this node of the branches was not completed And 98, and the pulse of GII 2 through the element And 99. In addition, the analysis start signal is fed to the input of the delay element 88 and to the read input of the memory node 73. There is a reading of the memory cell at the address of the number of the completed branch, i.e. read the number of the end node of the branch. The code of the read node number from the output of the memory node 73 is fed to the address inputs of the memory node 77 of the first output branch and to the information inputs of the register 80 of the end node. After a delay time sufficient for reading, the AND function for all the branches included in it is informed.

In this case, the search signal of the interruption from the pole 39 through the element OR 17 enters the single input of the trigger 11 and simultaneously through the pole 55 to the input of the OR element 118 of the branch search model 116 of the block of 4 models of 25 branches. From the output of the element OR 118, the signal is fed to the inputs of the elements And 107 (1) and 108 (1) of the first model of the branch. If the branch model has completed the process of modeling a branch that is still

formations from memory node 73, the signal was not analyzed, the trigger of the beginning of the analysis of the branch 106 goes to one state, and the equalizing input of the register 80 of the end node and to the read input of the memory node 77. By this signal, the number of the end node of the branch is written to the register 80 and the number of the first branch entering this node is read from the branch 77 of the memory. The code of the number of the first incoming branch from the output of the memory node 77 enters through the OR element 93 to the information input of the register 79 of the incoming branch and is written into it on the first pulse GII1 arriving at the control input of the register from the output of the AND 98 element. the code of the number of the first incoming branch goes through pole 35 and the elements OR 14 and 18 to the address input of the memory block 7 of the control unit 1, to the address input of the memory node 75 of the incoming branches and to the decoder 85. On the first GI2 pulse, the branch completion check signal from the output of the element And 99 act through the OR gate 96

the read input of the memory node 75, and through the AND 96 element at the input of the gateway a rez pole 37 and the OR 15 element to the memory node of the 75 incoming branches. To the input of the control unit 7 of the memory of the control unit 1. The mark of accomplishment, the signal from the output of the element And 108 again enters the input of the encoder address 117, as well as through the element

35 OR 120 generates an interrupt signal. The control unit 1, having received the model number of the branch and the interrupt signal, repeats all the described operations associated with the analysis of the accomplishment of the branch.

 If in block 4 of the branch models there are no models in which the trigger 106 is in a single state, the analysis process is not performed and the GI1 series pulses continue to flow.

5 through the element AND 22 to the node 29 for determining the longest path of the control unit 1 and to the drivers of the time interval of the branch models of the block 4 of the branch models.

If the signal of the mark of the fulfillment of the branch from the pole 45 has a single value, i.e. the simulation of this branch has ended, this signal gives permission for the passage of a pulse. GI2. The address inputs of the latter at this time receive the code of the number of the first incoming signal.

50

the tanna at the address of the first branch, from the output of the memory node 7 goes through pole 45 to the topology shaping unit 2, and through pole 46 to the topology shaping unit 3. If there is no label, the zero signal of the label from the pole 45 is through the element NOT 102 and the element OR 94 resets the trigger 94 to the zero state. In addition, the signal from the output of the element NOT 102 enters through the element OR 92 to the pole 39 of the interrupt search. The presence of a zero signal of the mark of the completion of a branch means that at least one of the incoming

I, therefore, in this node is not

 this branch node failed

It has been analyzed, trigger 106 is in a single state, and then

Yes, the signal from the output element And 108 again enters the input of the encoder address 117, as well as through the element

OR 120 generates an interrupt signal. The control unit 1, having received the model number of the branch and the interrupt signal, repeats all the described operations associated with the analysis of the accomplishment of the branch.

If in block 4 of the branch models there are no models in which the trigger 106 is in a single state, the analysis process is not performed and the GI1 series pulses continue to flow.

through the element 22 to the node 29 for determining the longest path of the control unit 1 and to the drivers of the time interval of the branch models of the block 4 of the branch models.

If the signal of the mark of the fulfillment of the branch from the pole 45 has a single value, i.e. the simulation of this branch is over, this signal gives permission for the passage of a pulse GI2 che

cut element AND 96 at the input of the gateway of node 75 of the memory of the incoming branches. On

the address inputs of the latter at this time receive the code number of the first incoming

Vetpi from register output 79. At the address of the first walking branch, from the memory node 75, the code of the number of the second branch entering the node is read. This code enters through the OR element 93 at the information inputs of the register 79 and is written into it with the arrival of the second pulse GI1. The next step is to poll the completion mark for this branch. The pdn branch has been completed, a transition is made to polling the accomplishment of the next branch entering the node in question, and so on.

The described process of analyzing the accomplishment of the branches continues until all the branches included in the node in question are surveyed. In this case, at the address of the last branch number, the code is read from the memory node 75.

X, defining the end of the list of incoming20 is over. The distinguishing feature of this node is the branches. The X code is written to the input branch register 79 and then fed to the input of the state decoder 85, generating a list end signal that passes through 25 elements OR 94 and 95 and sets the triggers 82 and 83, respectively, to zero and one. The signal from the output of the decoder 85 to the takedown moment is the absence of branch models occupied by the modeling process, in the presence of un-committed network nodes. At the same time, when checking the completion of the node, during the processing of an interrupt from the last model of the branch, which is engaged in the simulation process, the signal of checking the completion of the branch from pole 37 goes to

same to the first input of the element And 86, second to the first input of the element And 23 block 1

a swarm whose input is associated with the output of the comparison code decoder 86, which compares the codes stored in the register 81 of the end node of the network and in

register 80 of the end node of the branch. Re-35 about the absence of busy models

gister 81 stores the code of the network end node, and register 80 the code of the considered network node that formed the function of conjunction B is a given point in time. If the value of these codes does not match, the signal from the output of the decoder 85 goes through the element OR 89 to the read input of the memory node 76 of the first outgoing branch, to the address input of which, at this time, the generated network node number arrives. The process of preparing for the modeling of those branches that come out of this formed node begins.

If there are no cycles (contours) in the network, the described process of preparing branches for modeling, time modeling and analysis of branches that have been completed modeling, are alternated in the specified order and are repeated until the end node of the network is formed. In this case, the decoder of the codes of the unit of the topology formation unit 2 grants permission for the signal from the output of the decoder 85 to pass through the element

And 97 to the output pole 49, which corresponds to the end of the simulation of a given network. The signal from the pole 49 is fed to the input element And 12 of the control unit 1 and allows the issue to

external device is the value of the longest network path from node 7, and there is no signal that there are cycles from the output of the AND 24 element. All cells of node 6 of memory are reset.

If there is a contour in the network topology, the described network modeling process in the forward direction will stop at the time of the interrupt processing from the last branch, the simulation of which

is over. The distinguishing feature of the

This moment is the absence of branch models involved in the simulation process, in the presence of uncommitted network nodes. At the same time, when checking the completion of the node, during the processing of an interrupt from the last model of the branch, which is engaged in the simulation process, the signal of checking the completion of the branch from pole 37 goes to

management The second input of this element receives the resolving potential from the output of the element OR 120 of the block 4 models of branches, which signals

wei Since the considered node includes branches, the simulation of which has not yet occurred, there comes a moment when the zero signal of the completion mark from the node 7 of the memory of the control unit 1 through the NOT 28 element enters the third input of the AND 23 element. the signal, KOTopbtfi, is fed to the input of the trigger 10, setting it to one. In addition, the signal from the output of the element And 23 enters the block 3 forming the topology. The process of network modeling in the opposite direction begins. In this case, in memory node 6, labels will remain at those addresses that correspond to the numbers of the nodes belonging to the network contour, and to those addresses that correspond to the numbers of the nodes connected to the nodes of the contour by a chain of incoming branches.

The signal from pole 64 passes through the element OR 95 and sets the signal 131322304

The rep 83 of the topology formation unit 3 to a single state. The single state of the trigger 83 permits the passage of the pulse train GI1 through the element AND 100, and the pulse train GI2 - 5 through the pulse element AND 101. In addition, the signal from the pole 64 is fed to the input of the delay element 87 and to the read input of the memory node 72. The address inputs of the latter receive the code number 0 of the branch entering the network end node. Since in node 72 of memory, their end nodes are recorded at the address of the branches of the network being modeled, by the arrival of the signal

14

the resu of the number of the first branch entering the cynical node is reading the code of the duration of this branch from node 5. The O signal is written to the memory node 6 at the address of the number of the loaded node coming from the output of the OR element 21 of block 3 forming the topology through the pole 42. At the same time, the search signal of the free model from pole 60 is fed to the inputs of the elements AND 109 (1) and 109 (2) of the block 4 of the branch models. Since all branch models are free, the trigger 105 (1) of rereading from memory node 72 of the read model is in zero, the end network node code is. -This and the signal from the output element

the code enters through the element OR 90 110 (1) through the element 115 of delay pon the address input of the memory node 76 of the first incoming branch. After sufficient time to read information from memory node 72, a signal from pole 64 appears at the output of delay element 87 and enters through the OR 89 element to the input of the memory of memory node 76. On this signal, the code of the number of the first branch is read, input terminal network node. The code of the number of the first incoming branch from the output of the memory node 76 goes through the OR 91 element to the information input of the register 78 and is written into it by the first pulse GI1 arriving at the control input of the register from the output of the AND 100 element.

The recorded code of the first branch entering the end node from the output of the register 78 goes to the address input of the memory node 74, as well as via pole 31 and the OR element 12 to the address input of the memory node 9 and the information input of the memory node 8 of the numbers of the simulated branches of the block 1 control

Impulse ГИ2, shifted relative to impulse ГИ1, arrives on

steps into the trigger input 105 (1) and sets it to the unit state 20

This means that the simulation process is the first model of the branch. At the same time, the signal from the output of the element AND 110 (1) is fed to the first input of the element AND 110 (1) and through the element OR 113 (1) to the input of the encoder address 117. To the second input of the element 111 (1) through the pole 53 the length code of the branch, which is written to the driver 104 (1)

30 time interval. From the output of the address encoder 117, the code address code of the branch is fed to the address input of the node 7 of the memory of the numbers of the simulated branches of the control unit 1. By act

35, the branch number (in this case, the first branch entering the network end node) is recorded at the address of the selected branch model. This completes the preparation of the first incoming network node, the branch for the modeling process. Further, read to the address of the number of the first, entering into the final node, branches from

40

input schichit gang node 74 memory block 5 node 74 memory block 3 forming

Now, 3 topology formations, and at the address of the first branch entering the end node, is read into the number code of the second branch entering the same node. At the same time, by the pulse GI2, the search signal of the free model from the output of the element AND 101 through the pole 33 and the element OR 13 is fed to the read input of the node 9 of the memory, to the write input of the node

In the topology, the code of the number of the second branch entering the end node enters the information input of the register 43 and with the arrival of the second pulse, the GTI 50 is written to it. After that, the search for a model-free branch is again searched, the time code is written into its time interval generator, the memory number is written, to the delay element 20 of the simulated branch by control ad- dress, to the search search number 60 of the selected model models of block 4 models in node 8 of memory of block 1 of branches. By readout and control signal.

14

the resu of the number of the first branch entering the cynical node is reading the code of the duration of this branch from node 5. The O signal is written to the memory node 6 at the address of the number of the loaded node coming from the output of the OR element 21 of block 3 forming the topology through the pole 42. At the same time, the search signal of the free model from pole 60 is fed to the inputs of the elements AND 109 (1) and 109 (2) of the block 4 of the branch models. Since all branch models are free, the trigger 105 (1) steps into the input of the trigger 105 (1) and sets it to one

This means that the simulation process is the first model of the branch. At the same time, the signal from the output of the element And 110 (1) is fed to the first input of the element And 110 (1) and through the element OR 113 (1) to the input of the address coder 117. To the second input of the element And 111 (1), the branch duration code goes through pole 53 which is written to shaper 104 (1)

time interval. From the output of the address encoder 117, the code address code of the branch is fed to the address input of the node 7 of the memory of the numbers of the simulated branches of the control unit 1. Upon receipt of the signal from the output of the delay element 20, the branch number is recorded (in this case, the first branch entering the network end node) at the address of the selected branch model. This completes the preparation of the first branch of the network node to the modeling process. Further, read to the address of the number of the first, entering into the final node, branches from

In the topology, the code of the number of the second branch entering the end node enters the information input of the register 43 and with the arrival of the second pulse, the GTI 50 is written to it. After that, the search for a model-free branch is again searched, the duration code is written to its time interval generator, the recording process of preparing the peepers entering the network end node to the simulation process is carried out until the last branch from the list is read branches. At the address of its number in memory node 74, an X code is read, which is written into the register 78 of the topology generation unit 3.

The interrupt search signal with pole 40 enters the trigger input 11 of control unit 1 and sets it to the one state. Since in

 0 military direction. At the second input of the element And 27 there is a resolving potential from a single output of the trigger 10. Therefore, the signal to start the analysis of the completion of the branch and the moment under consideration there are no models

The branches terminating the simulation, the signal of the AND element 27 goes to the pole and the interrupt is absent and the trigger 48 and further to the block 3 of the formation 11 remains in the single state. topology.

In block 3 of the formation of the topology, the code of the number of the spreading branch with a field is 20

25

The unit state of the trigger 11 permits the passage of the pulses of the GI1 series to the counting input of the long path measuring section 29 and through the pole 54 to all the drivers 104 in the belt interval whose trigger 105 is in the single state. This continues until at least one of the time interval drivers 104 issues a signal to end the time modeling process.

The signals from the output of the formers 104 (1), 104 (2), ..., 104 (p) of the time interval are fed to the single inputs of the triggers 106 (1), 106 (2), ..., 106 (p)

Sa 43 arrives at the address input of the memory node 73, and the start signal of the analysis of the completion of the branch from the pole 47 arrives at the input of the flip-flop 82 and sets it to one state. In addition, the signal from the pole 43 is fed to the input of the delay element 88 and to the input to the reading of the memory node 73, where the coupling of the starting node number of the branch occurs (at the address of the number of the completed branch). The code of the read node number from the output of the memory node 73 goes to the address inputs of the memory node 77 of the first outgoing branch and to the information inputs of register 43 goes to the address input of the memory node 73, and the signal to start analyzing the branch from the pole 47 is sent on the trigger trigger 82 and sets it to a single state. In addition, the signal from pole 43 is supplied to the input of the delay element 88 and to the input to the readout of the memory node 73, where the starting number of the starting node of the branch is copied (at the address of the number of the completed branch). The code of the read node number from the output of the memory node 73 goes to the address inputs of the memory node 77 of the first outgoing branch and sets them to the information state register entries. Simultaneously, the signals from the outputs of the 35 ra 80 initial node. After the time of the formers 106 (1), 106 (2), ..., delays sufficient for reading 106 (p) are received through the OR 118 element and the information from the memory node 73, to the input of the interrupt search (1.1) first branch models. The interrupt processing stage begins, similarly to the starting node 80 histor, and to the input of the interrupt processing for simulating an access point 77 of the memory node. For this network behavior in the forward direction. The opsignal of the beginning of the branch execution analysis is fed to the control input of the resignal, the number of the starting node of the branch is written to register 80 and the code of the number of the branch leaving this node is read from memory 77 (45 address of the starting node of the branch). Further, this code enters control block 1, where the completion of the read branch is checked.

The model number of the branch that completed the simulation is determined. By this number, the code of the number of the completed branch is determined, a label 1 is written into the memory node at the address of the branch number. The code of the number of the accomplished branch goes to poles 43 and 44

the signal is written to the number of the starting node of the branch in register 80 and reading from the node 77 of memory (45 to the address of the number of the starting node of the branch) the code of the number of the first branch leaving this node. Further, this code enters control block 1, where the completion of the read branch is checked.

and further into the topological formation blocks, if the branch has not been completed, the process is hygiene. The interrupt signal from the time modeling pole 52 continues — it is fed to the input of the delayed-element element 19 further. If the first branch, claims, and after the delay time from the node in question, the cops 19 and 21 appear to have a single execution mark, the following code is read from the delay element 21 of the control unit 1 of the control unit 75 of the memory laziness. This signal is fed to the first inputs of the elements And 26 and 27. So. as trigger 10 is in single

branch and checks its performance. The process of checking the fulfillment of the branches emanating from the distance at the second input of the element And 26 there is a prohibiting potential from the zero output of the trigger 10. Therefore, the signal from the output of the element 21

the delay through the element And 26 does not pass and at the pole 47 there is a forbidding potential. This prevents the launch of the topology formation unit 2 in the network modeling in the opposite direction. At the second input of the element AND 27 there is a resolving potential from a single output of the trigger 10. Therefore, the start signal of the analysis of the execution of the downstream branch of the unit 3 of the formation of the topology is the code of the number of the branch with the field

Sa 43 arrives at the address input of the memory node 73, and the start signal of the analysis of the completion of the branch from the pole 47 arrives at the input of the flip-flop 82 and sets it to one state. In addition, the signal from the pole 43 is fed to the input of the delay element 88 and to the input to the reading of the memory node 73, where the coupling of the starting node number of the branch occurs (at the address of the number of the completed branch). The code of the read node number from the output of the memory node 73 is fed to the address inputs of the memory node 77 of the first outgoing branch and to the information inputs of the register 80 of the initial node. Through a delay time sufficient to read information from memory node 73, starting node 80 of the starting node, and to the input of the gateway of memory node 77. Therefore

ra 80 starting node. Through a delay time sufficient to read information from memory node 73, starting node 80 of the starting node, and to the input of the gateway of memory node 77. Therefore

The start analysis signal of the branch is fed to the control input of the PEP 80 of the initial node. Through a delay time sufficient to read information from memory node 73, starting node 80 of the starting node, and to the input of the gateway of memory node 77. Therefore

the signal is written to the number of the starting node of the branch in register 80 and reading from the node 77 of memory (at the address of the number of the starting node of the branch) the code of the number of the first branch leaving this node. Further, this code enters control block 1, where the completion of the read branch is checked.

If the branch is not completed, the process of temporal modeling continues with further. If the first branch originating from the node in question has a single fulfillment mark, the following code is read from the memory node 75

branch and checks its performance. The process of checking the fulfillment of branches proceeding from

looking at the node, continues until a branch with a zero mark is detected, or until all the results of the branch are decoupled. In the first case, the process of temporal modeling continues until the next model of the branch ends the modeling process, in case all the branches are analyzed. (1) single marks of accomplishment, preparation for the process of modeling the branches included in the node in question is carried out. After that, the process of temporary modeling continues.

The described processes of preparing branches for modeling, temporal modeling and analysis of branches whose modeling is completed (when modeling a network in the opposite direction), continue until all branches entering the completed nodes are completed. In this case, when processing an interrupt from the model of the branch that last completed the modeling process, the signal of checking the completion of the branch from pole 37 goes to the first input of Element I 2A, to the second input of the specified element is a signal of missing branch models from pole 51, and to the third input through the element NOT 28 is the zero tick mark from the node 7 of the memory. From the output of the element and 24 sig

When the cycle is present, the control unit is connected to output 35 of the corresponding pole 70. At the same time, in memory node 6, labels will remain at the addresses that correspond to the numbers of the nodes belonging to the network contour.

Correspondingly, to the information inputs from the first to fourth block of modeling branches, the output of checking the execution of a branch of the graph of the first formation unit of the topology is connected to the eighth input of the control unit, the output of the result of calculating the long path of the first formation unit of the topology is connected to the ninth input of the control unit the graph of the first block forming the topology is connected to the tenth input of the control block, the output of the number of the branch of the first block being prepared for modeling Neither the topology is connected to the eleventh input of the control unit, the output of the search for the free branch of the first block of the formation of the topology. To determine the numbers of network nodes belonging to the circuit, they must be fed to the input pole 68, which is fed to the read input of the memory node 6. The presence of label 1 at certain addresses will determine the numbers of nodes belonging to the contour.

Claims (2)

Invention Formula A device for simulating directional graphs comprising a control unit, a first topology generation unit, a branch modeling unit, a clock generator, an input 50 Correspondingly, to the information inputs from the first to fourth block of modeling branches, the output of checking the execution of a branch of the graph of the first formation unit of the topology is connected to the eighth input of the control unit, the output of the result of calculating the long path of the first formation unit of the topology is connected to the ninth input of the control unit the graph of the first block forming the topology is connected to the tenth input of the control block, the output of the number of the branch of the first block being prepared for modeling neither the topology is connected to the eleventh input of the control unit, the search output of the free branch of the graph of the first unit for forming the device connection topology is connected to the input 55 of prices to the twelfth input of the control unit for the first unit of the formation of the topology; O five 0 0 five to the first informational note of the first formation unit, read input of the node numbers of the device’s graph contour is connected to the first input of the control unit, input of the contour labels of the device’s graph is connected to the second input of the control unit, input of the device graphs to the third input of the control unit, output of the labels the contour of the path on the device graph is connected to the first output of the control unit, the output of the indication of the presence of the device cycle is connected to the second output of the control unit, the output value The most recent path on the device graph is connected to the third output of the control unit, the first clock generator output is connected to the first clock input of the first topology shaping unit and the fourth input of the control unit, the second clock pulse generator output is connected to the second clock input of the first topology shaping unit, model number output The block of models of branches is connected to the fifth input of the control unit; the output of the sign of the absent models of the branch of the block of models of branches is connected to the sixth input of the control unit. control locus, interrupt output of the branch model block is connected to the seventh input of the control unit, outputs from the fourth to the seventh control unit are connected to the corresponding Correspondingly, to the information inputs from the first to fourth block of modeling branches, the output of checking the execution of a branch of the graph of the first formation unit of the topology is connected to the eighth input of the control unit, the output of the result of calculating the long path of the first formation unit of the topology is connected to the ninth input of the control unit the graph of the first block forming the topology is connected to the tenth input of the control block, the output of the number of the branch of the first block being prepared for modeling No topology is connected to the eleventh input of the control unit, the search output of the free branch of the first block of the topology generation unit is connected to the twelfth input of the control unit, the interrupt search output of the first topology generation unit is connected to the thirteenth input of the block 1413  pr) in T (, the ficMcpa boot code took 1 raf;) of the first formation unit Tonojioi-i was connected to even 1, | | rnadts r (im in (1 control unit, eighth, ninth and tenth outputs of the control unit are connected respectively to the second, third and fourth information inputs of the first topology formation unit, the control unit contains four nodes of the memory, five AND elements, two triggers a HE element, three delay elements and a measuring unit of the longest way, and first of all go through the fifth control unit of the connecting element f5 and connected to the counting respectively, to the read input of the first memory node, the information input of the second memory node, the information input of the first memory node, the first input of the first And element and the address input of the third memory node, the sixth input of the control unit is connected to the first inputs of the second and The third And elements, the seventh input of the control unit is connected to the read input of the third memory node, the input of the first delay element and the input of setting the first trigger to zero, the eighth input of the control unit is connected to the second input of the second And element, the ninth The 30 input of the control unit is connected to the first input of the fourth element I, the first output of the control unit is connected to the output of the first memory node, the output of the third element I is connected to the 35 input of setting the first trigger to zero and the second output of the control unit whose third output is connected to the fourth output element I, the fourth input of the first trigger, the output of the node measuring the longest path is connected to the second input of the fourth element I, characterized in that in order to increase the reliability of the operation of the device by controlling the loop On the graph, it additionally contains a second topology shaping unit, the first and second outputs of the clock generator are connected respectively to the first and second clock inputs of the second topology shaping unit, the output of the number of the topology shaping unit being prepared for modeling is connected to the fifteenth input of the control unit, the output of the search for the free branch of the second block forming the topology is connected to the sixteenth input of the control block; the output of the number of the analyzed branch of the second block of the pho mation topology connected to the seventeenth entry of the control unit, the output verify achievements The lateral output of the control unit of the sub-40 branch of the second shaping unit is accurate to the output of the fourth memory node, the output of the first element I is connected to the input of the long-distance measuring unit and the fifth output of the control unit. gently connected to the eighteenth input of the control unit, the interrupt search output of the second topology shaping unit is connected to the nineteenth output of the control unit connecting the input of the network control unit, output The seventh output of the control unit is connected to the read input of the fourth memory node, the address input of the first memory node and the input of the second delay element of the control unit, the output of the third trigger. the second memory node is connected to the eighth output of the control unit; the output of the second memory node is connected to the input of the NOT element and the ninth output of the control unit; the tenth output of the control unit is connected to the output of the fifth And element, the inverse output of the first 55 BUT trigger go Podkkim to and to p r pomu pkhodu The fifth And element, the first delay element is connected to the recording input of the second memory and the input of the third delay element, the output of the second trigger is connected to the second input of the first And element, the output of the second delay element is connected to the information input of the third memory node, the third element the delay is connected to the second input of the fifth element I, the output of the element is NOT connected to the third input of the second and second input of the third element I, the output to the second input of the first trigger, the output of the long-distance measuring node Connected to the second input of the fourth element I, characterized in that in order to increase the reliability of the device by controlling the presence of circuits on the graph, it additionally contains a second topology generation unit, the first and second outputs of the clock generator are connected respectively to the first and second clock inputs of the second the topology shaping unit, the output of the number of the branch of the second topology shaping unit being prepared for modeling is connected to the fifteenth input of the control unit, the search output is free The second branch of the topology unit is connected to the sixteenth input of the control unit, the output number of the analyzed branch of the second topology unit is connected to the seventeenth input of the control unit, the output of the verification test gently sloping is connected to the eighteenth input of the control unit, the interrupt search output of the second topology shaping unit is connected to nineteen The number of the loaded node of the graph of the second topology shaping unit is connected to the twentieth input of the control unit, the input number of the final branch of the device graph is connected to the first information input of the second topological shaping unit, the eleventh, twelfth and thirteenth outputs of the control unit are connected respectively to the second, third and fourth information input of the second topology shaping unit, the fourteenth control unit output is connected the sixth element AND and seven OR elements are additionally entered into the control unit; moreover, the eleventh and fifteen inputs of the control unit are connected to the first and second inputs of the first OR element, the twelfth and sixteenth the inputs of the control unit are connected to the memory node, the outputs of the elements OR responsibly to the first and second inputs of the second element OR, the tenth and seventeenth inputs of the control unit are connected respectively to the first and second inputs of the third element OR, the eighth input of the control unit is connected to the first input of the fourth element OR, the eighteenth input of the control unit is connected to the second input of the fourth element OR and the third input of the third element AND, the fourteenth and twentieth inputs of the control unit are connected respectively to the first and second inputs of the fifth element OR, the thirteenth and nineteen The control unit inputs are connected to the first one respectively. and the second inputs of the sixth OR element, the direct output of the first trigger is connected to the first input of the sixth AND element, the output of the third control element is connected to the second input of the sixth AND element, the output of the first OR element of the control unit is connected to the address input of the fourth memory node and the third recording input five 0 five from the second to the seventh are connected respectively to the input of the second delay element, the first input of the seventh OR element, the read input of the second memory node, the write input of the first memory node, the counting input of the second trigger and the address input of the second memory node, the output of the third memory node is connected to the second input of the seventh OR element and the eleventh output of the control unit, the output of the second memory node is connected to the twelfth output of the control unit, the output of the sixth element AND is connected to the thirteenth output of the control unit, the second output element And is connected to the fourteenth output of the control unit ()) w / j ten) wIZ ( 2.P 060. BC (1. "W / No. () -X cpgu; shg) a / p 5CH 01 go // g;