SU1564643A1 - Device for solving activity problems - Google Patents

Abstract

The invention relates to computing and can be used to explore paths in a network. The aim of the invention is to expand the functionality of the device by solving the task of commons. The device comprises a control unit, a topology generation unit, a network modeling unit and a synchronization unit. Before starting work, the topology formation unit adds, in the form of lists of numbers of outgoing branches of network nodes, numbers of incoming branches of network nodes, numbers of initial nodes of network branches and numbers of end nodes of network branches, information about the graph topology. After launch, the device implements a tagging algorithm for finding the commie's path, when information about the initial angle in all possible directions is issued, each bit of which is a mark of the message passing through the corresponding network node. 3 il.

Description

The invention relates to computing and can be used to explore paths in a network.

The purpose of the invention is to expand the functionality of the device by solving the comm

Figure 1 shows the functional diagram of the device; 2 is the same, the topology shaping unit; On FKG.Z - the same, block network modeling.

The device comprises a control block 1, a block 2 forming a /: topology, a block 3 of network modeling and a block 4 of synchronization.

Control block 1 contains a node

5 steps of branch duration, node

6 spam numbers of simulated branches ,. path measurement node 7, modeling modeling address node 8, branch branch number register 9, branch free model number register 10, interrupt trigger 11, modeling label generation trigger 12, branch number comparison node 13, node number comparison 14, 15 18 elements U, - elements AND 1 9 - 22, node 23 elements AND AND, elements OR 24 - 28, element III 29, delay elements 30 - 33.

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The output of the number of the end node of the branch of the topology shaping unit 2 is connected via pole 34 to the input of the node 18 of the elements AND control unit 1. The output of the number of the branch of the topology formation unit 2 being prepared for modeling is connected via pole 35 to the address input of the memory node 5 and to the input of the comparison circuit 13 of the control unit 1 — JQ penalty. The output of the search for a free model of the branch of the topology shaping unit 2 is connected via pole 36 to the read input of the memory node 5, to the input of the AND 21, 22 elements and through the OR element 55 27 to the input of the node 16 of the AND control unit 1. The output of the trait of the final branch of the network of the topology formation unit 2 is connected via pole 37 to the input of the element 22 of the control unit 1 20 pen. The interrupt search output of the topology shaping unit 2 is connected via pole 38 to a single input of the interrupt trigger 11 of the control unit 1.

The analysis of the execution of the branch of block 2 is connected via pole 48 to the same input of block 1, the output of the code length of the branch of block 1 is connected via pole 49 to the same input of block 3, the write output of the modeling marks of the node of block 1 is connected via pole 50 to the same input of block 3, output reading the modeling marks of the node is connected via pole 51 to the same input of block 3, the output address of the modeling labels of the node is connected via pole 52 to the same input of block 3, the clock output of block 1 is connected via pole 53 to the same input of block 3, The output of the search for a free model of the branch of block 1 is connected via pole 54 to the same input of block 3, the output of the attribute of modeling the branch of block 1 via pole 55 is connected to the same input of block 3, the output of the sign of the simulation of the node of block 1 is connected via a poi with the same input of block 3 25 5b to the same input of block 3,

the polling input of the device is connected via pole 57 to the same input of block 1, the first output of block 4 (outputting a series of GI1 pulses) through the pole

ley branches through the pole 39. The output of the permission to issue the result of the topology shaping unit 2 is connected via the pole 40 to the input of the node of the elements of the control unit 1. The output of the start number - JQ 58 is connected to the first clock input 35

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The node node of the branch of the topology shaping unit 2 is connected via pole 41 to the input of the comparison circuit 14 of the control unit 1,

The output of the load resolution of the last branch of the network of the block 3 models of branches is connected via pole 42 to the input of the element 22 of the control block 1. The output of the simulation label of the node of the block 3 models of branches is connected via pole 43 to the input of the element OR 28 and, through the element NO 29, to the input of the element AND 21 of the control block 1. The output of the branch simulation label is connected to the input of the OR element 25 via pole 44. The output of the model number of the branch of the block 3 branch models is connected via pole 45 to the address input of the memory node 6 and to the information input of registers 9 and 10 of the control block 1. The interrupt output of the block 3 model of branches is connected via pole 46 to the read input of the node 6 of the memory, to the setup input of the register 9, to the input of the delay element 33 and to the zero input of the trigger 11 of the control block 1.

The output of the number of the completed branch of block 2 is connected via pole 47 to the same input of block 1, output 45

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unit 2, the second output of block 4 (generates a series of pulses GI2) is connected via poles 59 and 60 to the second clock input of block 2 and to the first clock input of block 1, the third output of block 4 (generates a series of pulses GIZ) connected via pole 61 to the second clock input of block 1, the device start input is connected via pole 62 to the same input of block 2, the input of the branch number code originating from the initial network node of the device is connected via pole 63 to the same input of block 2 the input specifying the number of network nodes of the device is connected pole 64 to the same name The unit 3 input, the output of the attribute of the branch of the shortest path of the commie of unit 1 is connected via the pole 65 to the device's output of the same name, the output of the attribute of the branch belonging to the set of paths of the unit 1 is connected via pole 66 to the device's same output, the output of the weight of the unit's path is connected via the pole 67 to the same output device.

The topology shaping unit 2 contains the node 68 of the memory of the numbers of the initial nodes of the network branches, the node 69 of the block 2 analysis branch memory is connected via pole 48 to the same input of block 1, the output of the code length of the branch of block 1 is connected via pole 49 to the same input of block 3, The output of the recording of modeling labels of the node 1 is connected via pole 50 to the same input of block 3, the reading output of the modeling labels of the node is connected via pole 51 to the same input of block 3, the output of the address of modeling labels of the node is connected via pole 52 to o the same input of block 3, the clock output of block 1 is connected via pole 53 to the same input of block 3, the search output of the free model of the branch of block 1 is connected via pole 54 to the same input of block 3, the output of the characteristic of modeling the branch of block 1 via pole 55 is connected to the same input of block 3, the output of the attribute of the simulation of the node of the unit 1 is connected via po58 connected to the first clock input5

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unit 2, the second output of block 4 (generates a series of pulses GI2) is connected via poles 59 and 60 to the second clock input of block 2 and to the first clock input of block 1, the third output of block 4 (generates a series of pulses GIZ) connected via pole 61 to the second clock input of block 1, the device start input is connected via pole 62 to the same input of block 2, the input of the branch number code originating from the initial network node of the device is connected via pole 63 to the same input of block 2, the input of the number of network nodes of the device is connected across pole 64 to the same name The input of block 3, the output of the attribute of the branch of the shortest path of the commie of block 1 is connected via the pole 65 to the device's output of the same name, the output of the indication of the branch’s belonging to the set of paths of the unit 1 is connected via pole 66 to the same output of the device; 67 to the same output device.

The topology shaping unit 2 contains the node 68 of the memory of the number of initial nodes of the network branches, the node 69 of the memory of the final nodes of the CP-ti branches, the node 70 of the memory of the numbers of the outgoing branches of the network nodes, the node 71 of the numbers of the first output branch of the network nodes output branch register 72, initial node register 73 of the branch being prepared, final node register 74 being prepared branch, end node node 75 register, network node register 76, trigger 77, decoder 78, code comparison nodes 79 and 80, delay elements 81 - 85 , nodes 86-88 elements OR, el elements OR 89 - 91, elements Pi 92 - 95, element NOT 96.

Block 3 of branch models (FIG. 3) contains K branch models (where K is the number of paths passing through all network nodes) 97 and branch model search node 98. Numbers in brackets denote sequence numbers identical in their design and functional purpose of the blocks, nodes, elements and poles. Each model of branch 97 consists of a former 99 time intervals, triggers 100 and 101, 3j, And 102-108 cops, Node 109 elements And, element

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114 (K), formers 94 (|), 99 (2),

.... 99 (K) time intervals for the 3 MODOLRY branches are pre-zeroed. Triggers 1 and 12 bpock

1 control, trigger 7 of the topology formation unit 2, triggers 100 (1),

100 (2), ..., 100 (K) and 101 (1), 101 (2), ...

..., 10 (K) and formers 116 (1),

116 (2), .., 116 (K) resetting the model of a branch of a block of 3 models of branches are initially in the zero state. In the counter of nodes 113 (1), 115 (2), ..,

115 (K) of the network of the block of 3 models of branches is preliminarily entered a code, one less than the number of network nodes.

After the initial installation on the pole 63 of the topology shaping unit 2, the code of the branch number that goes to the node's node, received for this calculation for the initial network node, i.e. the number of which is recorded in the register 76 of the network. Thus, the initial network modeling node is determined by the address of the branch number in the memory node 68 of the initial node numbers of the topology generation unit 2.

At some point in time, the Start signal arriving at pole 62

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OR 110, delay elements 111 and 112.0 of the topology shaping unit 2, the projected node 113 of the marks memory of the simulated branches, the node tags memory 114, the counter of the network nodes 115, the branch model reset 116.

The node 98 of the search for models of branches of the block 3 models of branches contains the address encoder 117, the elements OR 118 and 119, the decoder 120 for writing labels, the decoder 121 for reading labels.

The device works as follows.

In nodes 68 - 71 of the memory of the topology formation unit 2, lists of the modeled network are entered in the form of lists. Registers 72 - 75 are pre-wrapped, and the code of the number of any network node adopted as the initial network modeling node is entered into the register 76 of the network node. In the node 5 of the memory of the durations of the branches of the control unit 3, information on the duration of the network branches, i.e. at the address of the number of each branch of the network, a code of its duration is recorded. Memory node 6, path measurement node 7, modeling mark generation node 8, registers 9 and 10 of control block I, memory nodes FROM (O, FROM (2), ..., 113 (K) and 114 (1) , 114 (2), ...,

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walks through the element OR 91 and sets the trigger 77 to the one state. The unit state of the trigger 77 permits the passage of a series of GI pulses (from the first output of block 5) through pole 58 and P-12 (from the second output of block 4 through pole 59) through elements 93 and 94, respectively. In addition, the Start signal from the input pole 62 is fed to the input of the delay element 81 and to the read input of the node 68 of the initial nodes memory. This signal in the memory node 68 reads information from the memory cell, the address of which is determined by the branch number received from pole 63. Since the branch is selected as leaving the initial network modeling node, the output of the memory node 68 the code of this node is generated, which through the node 87 of the elements OR is fed to the address input of the memory node 71 of the first output branch 7 and to the information input of the register of the initial node 73 of the prepared branch. After a delay time sufficient to read the information

from memory node 68, a Start signal appears at the output ;; a delay element and a chores signal arrives OR 89

81

unit 2 formation topology,

walks through the element OR 91 and sets the trigger 77 to the one state. The unit state of the trigger 77 permits the passage of a series of GI pulses (from the first output of block 5) through pole 58 and P-12 (from the second output of block 4 through pole 59) through elements 93 and 94, respectively. In addition, the Start signal from the input pole 62 is fed to the input of the delay element 81 and to the read input of the node 68 of the initial nodes memory. This signal in memory node 68 reads information from the memory cell, whose address is determined by the branch number received from pole 63. Since the branch is selected as coming out of the initial network modeling node, the output of the memory node 68 is formed the code of this node, which, through the node 87 of the elements OR, goes to the address input of the memory node 71 of the first outgoing branch 7 and to the information input of the register of the initial node 73 of the prepared branch. After a delay time sufficient to read the information

from memory node 68, a Start signal appears at the output ;; a delay element and a chores signal arrives OR 89

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to the read input of the memory node 71 and to the control input of the register 73. This signal from the memory node 71 reads the code of the branch number, which is the first in the list of branches leaving the initial network modeling node. The code of the number of this branch from the output of the memory node 71 through the node 86 of the elements OR enters the information input of the register 72 of the output branch and is written into it by the first pulse GI arriving at the control input of the register 72 from the output of the element 93, In addition, A given Start signal, which arrived at the control input of register 73, is recorded in it with the code of the starting node number of the branch. From the output of register 73, the code of the number of the initial node of the branch arrives at the output pole 41.

The recorded code of the first output branch from the output of the register 72 goes to the address input of the memory node 70, as well as via pole 35 to the address input of the branch 5 memory of the duration of the branches, to the information input of the node 6 of the memory of the number of simulated branches and to the input of the comparison circuit 13 control block 1

Then, the pulse GI2, shifted relative to the pulse GI1, from the output of the element And 94 is fed to the readout input of the memory node 70, and at the address of the first outgoing branch, the number of the second branch leaving the considered node is read. In addition, the pulse GI2 from the output of element AND 94 is fed to pole 36 and to the input of delay element 85..C the output of delay element 85, a signal delayed for a time sufficient to read information from memory node 70, through element OR 90 enters the read input of the node 69 of the memory of the numbers of the final nodes of the network branches. The address input of the memory node 69, the output of the node 88 elements OR at this time enters the code of the branch number, which is connected from the node 70 of the memory. From the memory node 69, the code number of the nodule node of the second branch being prepared is read. This code from the output of the memory node 60 enters the information input of the register 74 and is written into it upon arrival at the control input of the next pulse GI1 from the output of the element AND 93.

In block 1 of the control, the search signal for a free branch model from pole 36

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enters the input of the readout of node 5 of the memory of the duration of the branches, the input of the elements 21 and 22, and through the element OR 27 the input of the node 16 of the elements I. The other input of this node receives the code from the output of register 9 of the number of the spent branch model. Since the register 9 is zeroed at the moment in question, a zero code will be generated at the output of the node 16 elements, which through pole 51 enters the input of the decoder 121 for reading the marks of the block 3 of the branch models. Since a null code is present at the input of the decoder 121, no readout signal is generated on any of the decoder outputs and calls are made to nodes 113 (1), 113 (2), ..., PZ (K) of the memory of tags of the simulated branches and nodes 114 (1), 114 (2) ,, .., 114 (K) the memory of node labels will not be available. Therefore, at the outputs of nodes 114 (1), 114 (2), ..., 114 (K) of the memory, a zero potential will be present, which will give a low level potential at the pole 43. This potential through the NOT 29 element enters the input element And 21, to another input of which a signal is received to search for a free branch model from pole 36. At output of element 21, a high level signal is generated, which through element OR 24 enters input of delay element 30 and pole 54. In addition, the signal from pole 36 the input to the readout of the node 5 of the memory, is the reading of the duration n dgotavlivaemoy branch. The code for the duration of the branch from the output of the node 5 of the memory through the pole 49 enters the block 3 models of branches.

In block 3 models of the branches, the signal from pole 54 is fed to the inputs of the elements AND 104 (1) and 105 (1) of the first model 5, branch 97 (1). Since all models are free at the considered moment, the trigger 100 (1) of the first model of branch 97 (1) will be in the zero state, and the signal from the output of the element 105 (1) through the delay element 112 (1) will go to the single input trigger 100 (1), setting it to one. This means that the process of modeling the duration of a loaded branch by the first model of a branch is busy. At the same time, the signal from the output of the element And 105 (1) is fed to the input of the node 109 (1) of the elements And, to the other input of the pole 49 the code of the duration 0

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U1564643

tee prepared branch. From the output of the node 109 (1) elements And the code of the duration of the branch arrives at the information input of the generator 99 (1) time5

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interval and is entered into it as initial information. In addition, the signal from the output of the element And 105 (1) of the first model of the branch through the element OR 110 (1) is fed to the input of the encoder 1 1 7 the address of the node 98 search for models of branches. The address encoder 117 will form the code of the model number of the branch (in this case, the first), which will be

In this case, the output of the delay element 31 generates the signal of the first pulse of the GIZ series, which, through the element OR 27, enters the input of the node lb of the AND elements, to the other input of which the code from the output of the register 97 arrives. Since register 9 is currently in the zero state then the output of the node 16 elements is generated; the zero code, which through pole 51 enters the input of the decoder 121, reads the labels of the block of 3 m branches of branches. Since the input is decrypted

divide the duration of the first output -, s rarator 121 entered the zero code, then

branch node. From the output of the decoder 117, the code of the model number of the branch through the pole 45 enters the control unit 1.

In control unit 1, the code of the model number of the branch from the pole 45 is fed to the information input of registers 9 and 10 and to the address input of the memory node of the numbers of the simulated branches 6. The input from the recording of the memory node 6 receives a signal from the output of the element OR 24 delayed by element 30 time delays in the search for a free branch model in a block of 3 branch models. This signal in memory node 6 records the code of the branch number, arriving at the information input from pole 35, at the branch model number address, the duration of the branch has already been entered into the time interval generator. In addition, the signal from the output of the delay element 30 is fed to the setup input of the register 10 and writes into it the code of the model number of the branch, as well as to the single input of the trigger 12, setting it to the single state. The unit state of the trigger 12 permits the passage of the pulses of the GIZ series (from the third output of block 4 through the poles 61) through the element 19 and the element OR 26 to the counting 8 forming the address of the marks of the simulated branches and to the input of the delay element 31.

The first impulse of the GIZ series will set at the output of node 8 code 1, which through the node of elements OR 23 and pole 52 goes to the address input of nodes PZ (1), PZ (2), ..., 113 (K) of the memory marks of the simulated branches and nodes 114 (1), 114 (2), ..., 1I4 (K) of memory marks nodes

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all branch models 97 (1), 97 (2), -...,

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No signal is generated at any of the outputs of the decoder. The outputs of the decoder 121 are connected to the i readout inputs of nodes 1 13 (1), 113 (2), ..., 113 (memory tags of the simulated branches and nodes 1U (1), 1 14 (2), ..., 1 14 (K) memory of tags of nodes of models of branches 97 (97 (2), ".., 97 (K), therefore no signal is generated at any of the outputs of the indicated nodes of memory. Potential of the level of the label of modeling the node from the outputs memory nodes 114 (1), 114 (2.,., P4 (K)) through the pole 43 enters the input of the element OR 28 of the control unit 1.

After a time sufficient to organize the described processes in block 3 of branch models, the output of delay element 32 of control unit 1 generates a delayed pulse signal signal of a series of GIZ, which enters the input of node 15 of elements P Another input of this node receives a register output 10 where the number of the found free branch model is written (in this case, the first one) From the output of the node 15 elements AND the code of the branch model number through the pole 50 is fed to the input of the decoder 120 of writing marks of the block 3 branch models. At the first output of the decoder, which corresponds to the model number of the branch, a high level signal is generated, which enters the recording input of nodes 113 (1) of the memory of marks of simulated branches and labels of nodes 114 (1), as well as the input of the AND 108 (1) element of the first model branches 97 (1). According to this signal, node 13 (1) of the tags memory of the simulated branches records information from the input pole 55, and node 114 (1) of the count tags memory contains information from the pole. Qual. (S and IMPULSE, formed RYCHOCHO 1Lemengl II 108

97 (K) block 3 models of branches. After a time sufficient to generate a code at the output of node 8, the control unit 10

In the output of the delay element 31, the signal of the first pulse of the GIZ series is formed, which through the OR element 27 arrives at the input of the node lb of the AND elements, to the other input of which the code from the output of the register 97 arrives. Since register 9 is currently in zero state After that, a zero code is generated at the output of the node 16 elements, which through pole 51 enters the input of the decoder 121 for reading the labels of the block 3 of branch models. Since the input of the decrypt, s Rator 121 entered the zero code, then

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No signal is generated at any of the outputs of the decoder. The outputs of the decoder 121 are connected to the i readings of the nodes 1 13 (1), 113 (2), ..., 113 (K) of memory labels of the simulated branches and nodes 1U (1), 1 14 (2),. .., 1 14 (K) of memory marks of nodes of models of branches 97 (1) 97 (2), ".., 97 (K), therefore, no signal is generated on any of the outputs of these memory nodes. The low level potential of the node modeling tag from the outputs of the memory nodes 114 (1), 114 (2). ,., P4 (K) through the pole 43 enters the input of the element OR 28 of the control unit 1.

After a time sufficient to organize the described processes in block 3 of the branch models, the output of the delay element 32 of control block 1 generates a delayed pulse signal from the GIZ series, which is fed to the input of the node 15 of the Pi elements. To another input of this node, the code comes from the output of register 10, where the number of the found free branch model is recorded (in this case, the first). From the output of the node 15 elements And the code of the model number of the branch through the pole 50 enters the input of the decoder 120 of the recording of marks of the block 3 models of branches. At the first output of the decoder, which corresponds to the model number of the branch, a high level signal is generated, which enters the recording input of nodes 113 (1) of the memory of marks of simulated branches and labels of nodes 114 (1), as well as the input of the AND 108 (1) element of the first model branches 97 (1). According to this signal, node 13 (1) of the tags memory of the simulated branches records information from the input pole 55, and node 114 (1) of the count tags memory contains information from the pole. QUALITY (s and IMPULSE formed by RYCHOCHO 1lengl II 108

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on a signal from pole 56, decreases. on 1 code of the counter of nodes 115 (1).

In block 1 of control, pole 55 is connected to the output of the element OR 25. The first input of the element OR 25 is connected with point 48 of the output of the branch modeling tag, and at a given moment there is a low level potential on it. (in register 9 the zero code is written). The second input of the element OR 25 Receives a signal: from the output of the node 13 comparison of branch numbers. The inputs of the comparison node 13 are associated respectively with the output of the modeling mark address generation node 8 and with the pole 35. Thus, a signal is generated at the output of the comparison node 13 in the case where the address of the record of the modeling marks corresponds to the number of the Branch To be prepared. the output of the comparison node 13 will form a signal in the event that the branch number 1 is prepared for modeling. A single mark will be written to the node 113 (1) of the memory of the first model of branch 97 (1) of block 3 of the models in This is the first address.

Pole 56 is connected to the output of the OR element 28 of the control unit 1. The first input of the element OR 28 is connected to the pole 43 of the output of the node modeling label, where at the moment in question there is a low level potential (in register 9 a zero code is written, therefore there is no address branch models). The second input element OR 28 receives a signal from the output of the circuit 14 comparing the numbers of nodes. The inputs of the comparison circuit 14 are connected respectively to the output of the node 8 to form the address of the modeling marks and to the pole 41 of the starting node number of the branch being prepared for modeling. Thus, at the output of the comparison node 14, a signal is generated, provided that the entry address of the modeling marks will correspond to the number of the initial node of the branch being prepared for modeling. At the considered moment, the output signal of the comparison node 15 will be generated if the branch is prepared for modeling. whose starting node number is 1. In this case, a single label will be written to the memory node 114 (1) of the first model of branch 97 (1) of block 3 of branch models

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at the first address, and the node counter code 115 (1) of this branch model is reduced by,

The next impulse of the GIZ series, which comes from pole 61 through element 19, to the counting input of node 8 of forming the address of tags of simulated branches, sets code 2 at the node's output. This code through node 23 of the OR elements and pole 52 enters the address input of nodes 113 (1 ), 113 (2), ..., 113 (K) of memory of tags of simulated branches and nodes 114 (1), 1 14 (2), .. ,, P4 (K) of memory of tags of nodes of the block 3 models of branches. After a time sufficient to generate a code at the output of the node 8 of the control block i, the output of the delay element 31 generates a signal of the second pulse of the GIZ series, which through the OR element 27 enters the input of the node 16 of the AND elements, to another input of which the code leaves the register 97 Since the register 9 is currently in the zero state, the output of the 16 element node AND is the zero code, which through pole 51 enters the input of the decoder 121 for reading the marks of the block 3 of branch models. Since the zero code entered the input of the decoder 121, no signal is generated at any of the outputs of the decoder. The outputs of the decoder 121 are connected to the read inputs of the nodes 113 (1), 113 (2), .., 113 (K) memory tags of the simulated branches and nodes 114 (lJ, 114 (2), .. ,, 114 (K) memory these node marks, therefore, the low potential level of the node modeling label from the output of the nodes 114 (1), 114 (2), ..., 114 (K) through the pole 43 enters the input of the OR element 28 of the control unit 1, and the low potential level of the label modeling the branch from the output of nodes 113 (1), 113 (2), ..., PZ (K) of the memory of the block of models of branches through pole 44 enters the input of the OR element 25. block 1 of the control.

After a time sufficient to organize the described processes in block 3 of branch models, the output of delay 32 of control block 1 generates a signal of a delayed second pulse of a series of GIZ, which arrives at the exit of node 15 of the elements AND. 10, where the number of the found free branch model is recorded. From the output of the node 15 elements And the code of the model number of the branch through the pole 50 enters the input of the decoder 120 of the recording of marks of the block 3 models of branches. At its first output, which corresponds to the free model number of the branch, a signal is generated that arrives at the input of the recording of node 113 (1) of the memory labels of the simulated branches and labels of nodes 114 (1) of the first model of branch 97 (1). On this signal, a single label will be written to the memory node of the simulated branches at node 113 (1) if the branch number 2 is prepared for modeling, and a single label is written to the node 14 (1) of the tags memory at the second address if a branch is prepared for modeling, whose starting node number is 2.

The next impulse of the GIZ series will increase by 1 the node code 8 of forming the address of the tags of the simulated branches of the control unit 1 and the recording process

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dtsey from the initial network modeling node. As noted, the impulse of the G112 series. From the output of the element AND 94 of the topology shaping unit 2 is fed to the read input of the node 17 of the memory of the numbers of the output of the branches. At this moment, the code of the number of the first branch coming out of that node arrives at the address input of the node / 0 of the memory. The code of the number of this branch from the output of the memory node 70 through the node 86 of the elements OR is fed to the information input of the register 72, the output of our branch, and is recorded in it by the second pulse GI1 supplied to the control input of the register from the output of the AND 93 element. From the output of the register 72 The code of the second outgoing branch enters control unit 1 via pole 35.

In addition, the code of the second branch, leaving the initial modeling node, is read from the memory node 70 of the topology generation unit 2 via

tags modeling branches and labels Uz-25 Nodes 86 and 88 elements OR comes

The catch is repeated for a new address. The address of the node 69 of the SoM memory is recorded at the end nodes of the network branches. On

tags to the node 113 (1) of the memory of the tags my-input for the connection of the node 69 of the memory through

shared branches of the first model of branch 97 (1) at the address of the number of the branch being prepared for modeling and writing the zero mark to all other addresses, as well as writing a single label to node 114 (1) of the nodes of the first model of branch 97 (1) at the starting node number of the branch being prepared for the simulation, and the zero mark writing at all other addresses.

The cohorts of the GIZ series and the recording of modeling marks for branches and nodes will continue until a high level signal is generated at the output of the node 8 overflow output of the addresses of the simulated branches of control unit 1, which corresponds to the enumeration of all possible branch and node numbers. The signal from the overflow output of the node 8 goes to the zero input of the trigger 12 and sets it to the zero state. The zero state of the trigger 12 prohibits the passage of pulses of the GIZ series through the element And 19. In addition, the overflow signal from the output of the node 8 enters the reset input of this node, setting it to the zero state.

Consider the process of preparing for the simulation of the next branch

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dtsey from the initial network modeling node. As noted, the impulse of the G112 series. From the output of the element AND 94 of the topology shaping unit 2 is fed to the read input of the node 17 of the memory of the numbers of the output of the branches. At this moment, the code of the number of the first branch coming out of that node arrives at the address input of the node / 0 of the memory. The code of the number of this branch from the output of the memory node 70 through the node 86 of the elements OR is fed to the information input of the register 72, the output of our branch, and is recorded in it by the second pulse GI1 supplied to the control input of the register from the output of the AND 93 element. From the output of the register 72 The code of the second outgoing branch enters control unit 1 via pole 35.

In addition, the code of the second branch, leaving the initial modeling node, is read from the memory node 70 of the topology generation unit 2 via

ep 35 „

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the element OR 90 receives the signal of the first pulse of the GI2 series from the output of the element AND 94 delayed by the delay element 85. From the memory node 69, the code of the number of the end node of the second output branch is read. This code enters the information input of register 74 and is written into it by the second impulse of the GI1 series, which arrives at the setup input of the register from the output of element AND 93. From the output of register 74, the code of the number of the end node of the second branch leaving the initial node of the simulation through pole 34 enters unit 1 control. In addition, in block 1 of the control from the output of the element I 94 through the pole 36 receives the second impulse of the series GI2.

In the control unit 1, the search signal for the free branch model from the pole 36 is fed to the read input of the branch 5 memory of the duration of the branches, the address number of which is the second outgoing branch arrives at the address input from the policy 35. Read the code of the duration of this branch through the pole 49 enters the block 3 models of branches. In addition, the search signal for a free branch model from the pole 36 through the OR element 27 is fed to the input of the node 16 of the IT gate, to the second input of which

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code from the output of the register U /. At the considered moment, the zero code is stored in the register 9, therefore, as noted, the reading of information from the memory nodes of the node 114 of the block of the model of branches is not performed, and at the pole 43 there is a zero potential. This potential through the element 29 of the control unit 1 is fed to the input of the element 21, allowing the search signal of the free branch model to pass from the pole 36 through the element OR 24 to the output pole 54 and further into the block 5 of the branch models. (five

In block 3 models of branches, the search signal for a free model of a branch from pole 54 enters the inputs of the elements AND 104 (1) and 105 (1) of the first model of branch 97 (1). Since the trigger 100 (1) of the first branch model is in the single state, meaning the first branch model is busy, the signal from the output of element 104 (1) goes to 156464J) 6

This model of the branch in the register 10. In addition, the signal from the output of the delay element 30 of the control unit 1 is fed to the single input of the trigger 12, setting it to the single state. The unit state of flip-flop 12 permits the passage of pulses of the GIZ series through element 19 and the formation of marks of simulated branches and marks of nodes. In addition, each

the pulse GIZ increases by G the code of the node 8 forming the address of the modeling marks. The code from the output of node 8 through the node of the elements OR 22 and the pole 52 enters the address input of the memory nodes 113 (1), PZ (2), ..., PZ (K) and 114 (1), 1 14 (2), ..., P4 (K) all, branch models 97 (1), 97 (2), ..., 97 (K) of block 3 models of branches. Next, each pulse GIZ (delayed by the delay element 31 of the control unit 1, through the OR element 27 enters the input of the node 16 elements AND, forms a zero code at the gateway 54 (2) of the second model of branch 97 (2). 25 Through the trigger 100 (2) of this model, the branch 51 enters the input of the decoder 121 of reading labels of the block of model 3 branches. The zero code determines the absence of a read signal at 30 all nodes 113 (1), 113 (2), ..., 113 (K a) memory of marks of simulated branches and nodes 114 (U, 114 (2), ..., P4 (K) of memory marks of nodes. The absence of a read signal will determine zero the potential at the poles 43 and 44 of block 3 is modulated in the zero state, therefore, a high level signal is generated at the output of the element 105 (2). This signal is fed to the input of the node 109 (2) elements AND, and into the driver 99 (2) time intervals the code of the duration of the second branch is recorded leaving the initial modeling node. In addition, the signal from the output of the elements 105 (1) through the delay element 112 (2) enters the single input of the trigger 100 (2) and sets it to the one state. The code of the number of the second model of the branch, which from the output of the encoder through the pole 45 enters the control unit, is formed on the same signal by the encoder 117 of the address of the branch model search 98.

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lei branches. In addition, each GIZ pulse, the delayed delay elements 31 and 32 of control unit 1, enters the input of node 15 of the elements AND, generates at the output of the code the number of the branch model where the duration of the branch being prepared for modeling was recorded (in this case code 2 ) “This code, via the control unit 1 control unit, code number 45, pus-50, is fed to the decoder 120 of the recording of marks of the block 3 of branch models. On the second output of the decoder 120, which corresponds to the model number of the branch branch model from the pole h.) Is fed to the address input of node 6, memory numbers of the simulated branches, to the information inputs of registers 9 and 10 numbers of the used branch model and e number; about the free model. The entry of the recording of node 6 of the memory and the setup input of register 10 receive a delayed search signal of the free branch model from the output of the delay element 30. The first 55 or one label to the nodes of the memory card records the number of the second number - ti 113 (2) and 114 ( 2) at the address of the outgoing branch to the memory node 6 by t PblS, the code of the node 8 is defined as the address of the number of found free rubbing of the modeling marks of block 1, branching and setting the code of the control number. A single label of the model generates a signal arriving at the recording inputs of the node 113 (2) of the tags memory of the modulated branches and node 14 (2) of the memory of the tags of the nodes, as well as at the input of the And 108 element of the second branch model. Recording occurs. The zero pulse GIZ increases by G the code of the node 8 forming the address of the modeling marks. The code from the output of node 8 through the node of the elements OR 22 and the pole 52 enters the address input of the memory nodes 113 (1), PZ (2), ..., PZ (K) and 114 (1), 1 14 (2), ..., P4 (K) all, branch models 97 (1), 97 (2), ..., 97 (K) of block 3 models of branches. Next, each pulse GIZ (delayed by the delay element 31 of the control unit 1, through the OR element 27 enters the input of the node 16 elements AND, generates at the output of the node a zero code, which through pole 51 enters the input of the decoder 121 of reading the marks of the block 3 of branch models. determines the absence of a read signal at 0 all nodes 113 (1), 113 (2), ..., 113 (K) of the memory of tags of the simulated branches and nodes 114 (U, 114 (2), ..., P4 (K ) Node mark memory. The absence of a read signal will determine the zero potential at the poles 43 and 44 of the block 3 mode 5

0

lei branches. In addition, each GIZ pulse, the delayed delay elements 31 and 32 of control unit 1, enters the input of node 15 of the elements AND, generates at the output of the code the number of the branch model where the duration of the branch being prepared for modeling was recorded (in this case code 2 ) “This code is through the labels of the block of 3 branch models. At the second output of the decoder 120, which corresponds to the model number of a branch or one label to the nodes of memory 113 (2) and 114 (2) at the address that is determined by the code of the modeling labeling node 8 of the control unit 1. A single label of a model or a single label to the nodes of memory 113 (2) and 114 (2) at the address that is determined by the code of the modeling label generation node 8 of the control unit 1 of the control. A single label of the model generates a signal arriving at the inputs of the recording of node 113 (2) of the memory of labels of modulated branches and node 14 (2) of memory of the labels of nodes and also at the input of the And 108 element of the second model of the branch. Zero recording occurs

Driving branches to the node 113 (2) of the memory of the block 3 of the models of the branches is recorded when a high level signal is generated at the output of the comparison node 3 of the control block 1. This will happen when the code of the node 8 for generating the address of the modeling marks coincides with the code of the number of the branch being prepared, i.e. in this case, a single label is written to the node 113 (2) of the memory of the second model of branch 97 (2) of the block 3 models of branches at the address of the given branch o The single label of nodes in node 114 (2) of the memory of block 3 of models of branches is recorded in that case when the output of the comparison node 14 of the control unit 1 generates a high level signal. And this will happen in the case when the code of the node 8 forming the address of the modeling coincides with the code of the starting node number of the branch being prepared, i.e. In this case, a single label is written to the memory node of the second model of branch 97 (2) of block 3 of branch models at the address of the starting node number of the second branch. The counter code of nodes 115 (2 networks of the second model of branch 97 (2) is decremented by 1.

The process of forming labels of simulated branches and node labels continues until such time as a high level signal is generated at the overflow output of node 8 of control unit 1; the specified signal arrives at the zero input of trigger 12, sets it to zero the This prohibits the passage of GIZ pulses through an E 19 element. The process of preparing for the simulation of the secondary

Dov will generate a signal for the end of the list of outgoing branches. This signal e from the output of the decoder 78 arrives at the zero input of the trigger 7, setting it to the zero state. The zero state of the trigger prohibits the passage of GI1 and GI2 pulses through AND 93 and 94 elements respectively. In addition, the signal from the output of the decoder 78 goes to pole 38. From the pole 38, the interrupt search signal goes to the single input of trigger 11 of control unit 1, setting it to a single state, as well as through pole 39 to the input of the OR element 118 of the node 98 of the search for models of branches of the block 3 models of the branches, as well as to the input of the dumping drivers 116 (1), 1 1 6 (2),, .., 116 (K) all models of branches. From the output of the OR 118 element, the interrupt search signal is fed to the inputs of the AND 102 (1) and 103 (1) elements of the first model of branch 97 (1). Since at the moment in question the branches emerging from the initial network modeling node and the models of the branches that have completed the modeling process are not prepared, the interrupt trigger 101 (1) of the first model of branch 97 (1) will be in the zero state the potential from the zero output of the trigger 101 (1) is fed to the input of the element AND 102 (1), and at the output of the element a search interrupt signal is generated, which through a pole (2.1} enters the inputs of the elements 102 and 2 (2) and 103 (2) the second model of branch 97 (2). Since the interrupt trigger 101 (1) is second mode If branch 97 (2) is also in the zero state, the interrupt search signal generated at the output of element 102 (2) will go through the poles (3.1) to the inputs of elements

a swarm of a branch going out of the initial

network modeling node, on this one, And 102 (3) and 103 (3) of the third model of branch 97 (3), etc. to K. Since at the considered moment there are no interrupt triggers 101 (1), 101 (2), ..., 101 (K), which are in a single state, then none of the elements 103 (1), 103 (2), 103 (K) interrupt signal is not generated. Therefore, at the output of the element OR 119 of the node 98 is searched.

This is how the branches leaving the initial network modeling node are prepared for the time modeling process of their duration until the last branch from the list of output branches is prepared. After that, its address in the node 70 of the memory of the output numbers the branches of the topology shaping unit 2 will read the X code, which will be written into the register 72. The output of the register 72 is connected to the decoder 78 of the state X, where by comparing

55

As for the models of branches, the inputs of which are connected to the outputs of the elements And 103 (1), 103 (2), ..., SW (K), the potential of low level will be present. This potential through poypus 4b enters the zero input of Tpmicpi II block

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Dov will generate a signal for the end of the list of outgoing branches. This signal from the output of the decoder 78 arrives at the zero input of the trigger 7, setting it to the zero state. The zero state of the trigger prohibits the passage of GI1 and GI2 pulses through AND 93 and 94 elements respectively. In addition, the signal from the output of the decoder 78 goes to pole 38. From the pole 38, the interrupt search signal goes to the single input of trigger 11 of control unit 1, setting it to a single state, as well as through pole 39 to the input of the OR element 118 of the node 98 of the search for models of branches of the block 3 models of the branches, as well as to the input of the dumping drivers 116 (1), 1 1 6 (2),, .., 116 (K) all models of branches. From the output of the OR 118 element, the interrupt search signal is fed to the inputs of the AND 102 (1) and 103 (1) elements of the first model of branch 97 (1). Since at the moment in question the branches emerging from the initial network modeling node and the models of the branches that have completed the modeling process are not prepared, the interrupt trigger 101 (1) of the first model of branch 97 (1) will be in the zero state. from the zero output of the trigger 101 (1) enters the input of the element AND 102 (1), and at the output of the element a search interrupt signal is generated, which through the pole (2.1) enters the inputs of the elements 102 and 102 (2) and second (2) branch model 97 (2). Since the interrupt trigger 101 (1) second mode and branches 97 (2) also is in the null state, then the search interrupt signal generated at the output of element 102 (2), through the pole (3,1) will go to the inputs of elements

s

50

As for the models of branches, the inputs of which are connected to the outputs of the elements And 103 (1), 103 (2), ..., SW (K), the potential of low level will be present. This potential, through the 4us, goes to the zero input Tpmicpi II of control unit 1, confirming its single state. The unit state of the trigger 11 permits the passage of the GI1 series pulses through the AND 20 element to the counting input of the path measurement unit 7 and to the pole 53. With the pole 53, the measuring series pulses arrive at the input of the AND elements 106 (1), 106 (2),

. , U6 (K) of all models of branches 97 (1), 1Q of the Creme of this, signal of pre 97 (2), ..., 97 (K) of block 3 of models of branches and pass to the shapers 99 time intervals of those models branches 97, in which the trigger trigger 100 is in a single state. With the arrival of each pulse of the measuring series, the code of the time interval formers decreases by 1, and the path measurement node sums up the time simulation. With the arrival of the number of pulses of the measuring series, equal to the minimum code recorded in any driver, the latter is zeroed and gives a signal that the temporal simulation of the branch duration is completed.

The signals from the outputs of the formers of the time intervals 99 (1), 99 (2),.,., 99 (K) are fed to the single inputs of the trigger 101 (1), 101 (2) ,, .., 101 (K), set them into one state, as well as to the inputs of the OR element 118 of the branch model search node 98.

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jerking formed at the output of the element 103 of the block 3 models of branches, through the element OR 130 arrives at the input of the address encoder 317 of the branch model search node 97. From the output of the encoder 117, the code of the model number of the branch setting the interrupt through pole 45 enters control block 1 . In addition, the signal generated at the output of the element And 103 of the block 3 of the branch models is fed to the input of the reset generator 116 of the branch model, at which its trigger is set to one state, and also through the element of the 251I1 holder enters the zero input of the interrupt trigger 101, set it to the zero state.

In the control unit 1, the interrupt signal from the input pole 46 is fed to the read input of the node 6 of the memory of the numbers of the simulated branches and to the installation input of the register 9 of the number of the spent branch model. The address of the input node 6 memory and the information

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From the output of the element OR 118 the signal of the search-35 ration input of the register 9 from the pole 45

Each interrupt through the pole (1,1) enters the inputs of the elements AND 102 (1) and 103 (1) of the first model of branch 97 (1). If the interrupt trigger 101 (1) of the first model of branch 97 (1) is set to one, the output of element 103 (1) generates an interrupt signal s which, via pole (1.2), enters the input of element OR 119 of branch model search 98 . Otherwise, an interrupt search signal will be generated at the output of AND 102 (1) of the first model of branch 97 (1). This signal through the pole (2,1), is fed to the inputs of the elements And 102 (2) and 103 (2) of the second model of the branch 97 (2). If the trigger 101 (2) of the second model of branch 97 (2) is also in the zero state, the interrupt search signal generated at the output of element 102 (2), through the pole (3.1), is fed to the inputs of elements AND 102 (3) and 103 (3) of the third mode, the branches 97 (3), etc., until a model of the branch is found, in which

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Receives the code of the model number of the branch that triggered the interrupt. By writing the code of the number of the spent branch model to register 9 and reading information from the memory cell of the memory node 6 to the address of the branch model number, i.e. reading the code of the branch number, the simulation of the duration of which is completed. The branch number num- ber from the output of the memory node 6 goes to pole 47. In addition, the interrupt signal from pole 46 goes to the zero input of the trigger 11, sets it to the zero state, and the same to the input of the delay element 33. sufficient for reading the branch number code from the memory node 6, at the output of the delay element 3 a signal is generated to begin the analysis of the completion of the branch, which via pole 48 enters the topology generation unit 2.

In block 2 of the formation of the topology, the signal to start the analysis of the completion of the wind

interrupt trigger 101 is set to one. The interrupt signal generated at the output of the AND element 103 of this branch model is fed to the input of the OR element 119 of the branch model search node 98. From the output of the element OR 119, the interrupt signal through the pole 46 enters the control unit 1 of the “Creme of this” signal

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jerking formed at the output of AND 103 of the block of 3 models of branches, through the OR 130 element enters the input of the address encoder 317 of the branch model search node 98. From the output of the encoder 117, the code of the branch model number that placed the interrupt goes through pole 45 to control block 1. In addition, the signal generated at the output of the element And 103 of the block 3 models of branches is fed to the input of the generator 116 of resetting the branch model, setting its trigger to one state, and also through the holding element 1I1 to the zero input of the interrupt trigger 101, setting it to zero.

In the control unit 1, the interrupt signal from the input pole 46 is fed to the read input of the node 6 of the memory of the numbers of the simulated branches and to the installation input of the register 9 of the number of the spent branch model. To the address input of node 6 of memory and to information0

ration input of register 9 from pole 45

Receives the code of the model number of the branch that triggered the interrupt. The code of the number of the spent branch model is recorded in the register 9 and the information is read from the memory cell of the memory node 6 at the address of the branch model number, i.e. reading the code of the branch number, the simulation of the duration of which is completed. The branch number code from the output of the memory node 6 goes to pole 47. In addition, the interrupt signal from pole 46 goes to the zero input of the trigger 11, sets it to the zero state, and also to the input of the delay element 33. After a time sufficient for reading the code of the branch number from the memory node 6, the output of the delay element 33 generates a signal to start the analysis of the completion of the branch, which through pole 48 enters the topology generation unit 2.

In block 2 of the formation of the topology, the signal to start the analysis of the accomplishment of the branch

from the pole 48 enters the input of the delay element 83 and through the OR element 90 to the read input of the node 69 of the memory of the numbers of end nodes of the network branches, to the address input of which from the pole 47, the branch number code enters the address input 88, the simulation of which duration is over. The information is read from the cell of memory node 69, where the number of the terminal node of the branch in question is recorded. From the output of the memory node 69, the code of the number of the end node of the branch arrives at the information inputs of the register 74 of the end node of the branch being prepared and the register 75 of the branch being analyzed. After a time sufficient to read information from memory node 69, the output of delay element 83 generates a high level signal, which is fed to the input of delay element 84 and to the setup input of register 75. The end node code of the processed branch is written to register 75. register output 75 is the code of the number of the end node of the branch through the node 87 elements. OR is fed to the address input of node 7J of the memory of the numbers of the first branch, Through a time sufficient to record the number of the branch's final node in register 75, the output of delay element 84 generates a high level signal that enters the input of the element 92, To another the entry of this element in the case where the code of the end node of the branch being processed is not equal to the code of the node number of the network adopted as the initial node

network modeling (modelcropping process)

The vanity is not at the end point and there is a zero potential at the output of the code comparison node 80), the resolving potential comes from the output of the element HE 96.

At the output of the element 92 and the signal is formed, which through the element OR 89 enters the input of the readout of the memory node 71 and the installation input of the register 73, and through the element OR 91 - to the single input of the trigger 77. The trigger 77 is set to one, allowing pulses GI1 and GI2, respectively, through elements AND 93 and 94. This completes the stage of processing the interrupt from the branch model, which has completed the process of modeling the branch duration, and the preparatory stage for the mod

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the delimitation of the branches going out and: the end node of the processed year,

The signal that enters the readout input of the memory node 71 performs the readout of the memory cell at the address that arrives at the address input from the output of the register 75 of the end node of the analyzed branch through the element OR 87, i.e. the first branch in the list is read out, leaving the end node of the branch, the simulation of the duration of which is completed. The code of the number of the read branch and from the output of the memory node 71 through the node 86 of the elements OR is fed to the information input of the register 72 of the output branch and is written into it by the first pulse GI arriving at the control input of the register from the output of the AND 93 element. the code of the number of the first output branch from the output of the node 71 of the memory of the topology generation unit 2 through the nodes 86 and 88 of the elements OR is fed to the address input of the node 69 of the memory of the numbers of the final nodes of the network branches. The input to the readout of the specified node through the element OR 90 receives a signal from the delay element 82 delayed by a time sufficient for reading information from the memory unit 71. This signal from memory node 69 reads the code of the number of the end node of the first outgoing branch. This code from the output of the memory node 71 enters the information input of the register 74 and is written into it by the first GI pulse arriving at the register setup input from the output of the AND 93 element. From the register 74 output, the code of the end node number of the first output branch through the pole 34 enters in unit 1 control. In addition, the signal that arrived at the setup input of the register 73 records the code of the initial node of the first output branch of register 75. From the output of the register 73, the code of the number of the starting node of the branch goes to the output pole 41.

The recorded code of the first output branch from the output of the register 72 goes to the address input of the memory node 70, and also through the output pole 35 of the topology shaping unit 2 to the address input from the node 5 memory of the branch duration, the information flow took into account 6 memory numbers of the simulated set - Weigh and on the ROCKET of the comparison unit I t of the control unit 1.

Then, the pulse GI2, shifted relative to the pulse GI1, from the output of the element AND 94 of the topology shaping unit 2 is input to the readout input of the memory node 70, and at the address of the first outgoing branch, the number of the second branch leaving the considered node is read. the signal GI2 from the output of the element I 94 through the pole 36 enters the control unit 1. In block 1 of the control, the search signal for the free branch model from the pole 36 is input to the readout of the node 5 of the memory of the branches, to the input of the AND elements 21 and 22 and through the OR element 27 to the input of the node 16 of the elements I. To the other input of the specified node of the elements AND Register 9 receives the code of the model number of the branch, the interruption from which was processed last. At the output of node I6 of the elements I, a code of the specified model of the branch is formed, which through pole 51 enters the input of the decoder 121 of reading the marks of the block of 3 models of the branches. At the output of the decoder, which corresponds to the model number of the branch, a signal will be generated. The input to the read input of nodes 113 and 114 of memory of the specified model is vevi, as well as the input of element AND 107 To the address input of nodes 113 and 114 via pole 52 from the node 23 elements OR the control unit I receives the code generated at the output of the node 18 elements I. The first input of the node 18 elements I is connected to pole 34 and the code of the end node of the branch being prepared for modeling arrives at the other input of the node 18 elements AND act allowing a potential from the zero output of flip-flop 12. Thus, the output node of the AND 18 and thus on the address input of the memory nodes 113 and 114 models branch unit 3 is formed by the end node prepares to modeling code branch. Information is being read from the node memory 114 of the node tags of the branch model that completed the branch duration simulation at the address of the end node number of the branch being prepared for the simulation. And if a single label is read which means that this branch is included in the already passed network node, the high level signal from the node output

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five

45

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the memory 114 through the pole 43 and the element NOT 29 of the control unit 1 is fed to the input of the element 21 and prohibits the passage of the search signal of the free branch model from the pole 36 through this element.

In the case under consideration (with a single node label), a search signal for a free branch model can be formed at the output of element AND 22. This will occur if there are permissive signals at the inputs of element And 22 associated with pole 37 and pole 42. The resolving signal from pole 37 which is associated with the output of the node 79 of the comparison of the codes of the topology shaping unit 2, is formed when the codes recorded in registers 74 and 76, i.e. when the end node of the branch being prepared equals the initial network modeling node (the path closes at the starting point). A resolution signal at pole 42, which is associated with the combined output of AND 107 (1), 107 (2), ..., 107 (K) units of 3 branch models, will be generated if the counter of 115 nodes of the branch model network where the node label is read from will be reset to zero, and at its output an overflow, connected to the input of the element M Q / S, a high level signal is generated (the simulated path passes through all the nodes and the prepared branch closes it in the initial network modeling node) about

In the considered example, the search signal of the free model of the branch from the output of the element And 22, and when reading the node zero mark from the output of the element 21, through the element OR 24 enters the input of the delay element 30, as well as to the output pole 54.

If even at one of the poles 37 or 42 there is no enabling signal, and a single label is read from the node labels memory node 114 of the branch model block 3, the search signal for the free branch model is not generated, the branch duration is not entered into the branch time generator and the preparation the modeling branch ends there.

If the search signal of the free branch model is generated from pole 54, it is fed to the input of the elements AND 104 (1) and 105 (1) of the first model of the wind5

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vi 97 (1) block 3 models of branches. If the trigger 100 (1) of the first model of branch 97 (1) is in the single state (the model is occupied), the signal from the output of the AND 104 (1) element through the pole 54 (2) is fed to the input of the AND 104 (2) and 105 elements (2) a second model of branch 97 (2). If the trigger 100 (2) of the second model of branch 97 (2) is also in the unified JQ state, the signal from the output of the AND 104 (2) element via the pole 54 (3) is fed to the input of the AND 104 (3) and 105 elements ( 3) the third model of branch 97 (3), etc. until the first free model of

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A trigger in which the trigger 100 is in the zero state. In this model of the branch, the high level signal from the output of the element And 105 is fed to the input of the element And 109 and the driver of 99 time intervals of this model of the branch is entered the code of the duration of the prepared branch, which is fed to another input of the element 109 from the pole 49. In addition, the signal from the output of the 25th element of the AND 105 through the delay element 112 enters the cha inlet ™ of the rigger 100, setting it to a single state. Next, the signal from the output element And 105 through the element OR 110 is fed to the input of the encoder 117 address of the node 98 search for models of branches. At the output of the address coder, the code of the number of this free branch model is formed, which through pole 45 enters the control unit 1.

In control unit 1, the code of the branch model number from the pole 45 is fed to the address input of the node 6 of the memory of the number of the simulated branches, to the information input of registers 10 and 9 the number of the free branch model and the register number of the used branch model. At the considered time, the information input of the node 6 of the memory receives the code 45 of the number of the branch being prepared from crawl 35, and the recording input is sent a delayed signal of searching for a free branch model from the output of the delay element 30.

Record the number of prepared j-n

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Amoi branches in the memory node according to the address of the model number of the branch that will be used for its duration. In addition, the delayed search signal of the free model of the branch from the output of the element g g of the support 30 is fed to the set input of register 10, where the model number of the branch is written. Besides this, the delayed signal of the search for freedom40

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The model of the branch from the output of the delay element 30 is fed to the input of the trigger 12 for the formation of modeling marks. The process of recording the labels of the simulated branches in the y: begins; 1 1 3 memory and node labels in the memory node 114 of the block 3 models of branches.

The high level potential from the unit output of the trigger 12 of the control unit 1 enters the input of the element AND 19 and permits the passage of pulses of the accelerated series of GIZ from the pole 61 through the element 19 and the element OR 26 to the counting input of the modeling mark forming unit 8. The first impulse of the GIZ series will install at the output of node 8 code 1, which is fed to the input of circuits 13 comparing branch numbers and node numbers 14, as well as through node 23 of the OR elements and pole 52 to the address inputs of memory nodes 113 and 114 of all branch models 97 blocks 3 models of branches. In addition, the GIZ series signal, delayed by delay element 31 for a time sufficient to trigger node 8, passes through the OR element 27 and enters the input of node 16 elements I. The other model input of the specified node from register 9 output receives the branch model code that it ended modeling branch duration. The specified code from the output of the node 16 elements And through the pole 51 enters the decoder 121 read the marks of the node 98 search for models of branches of the block 3 models of branches. At the output of the decoder 121, which corresponds to the number of the spent branch model, a signal is generated that enters the input of the IZ memory nodes and 114 of the specified branch 97 model. The simulated branch tag from the memory node 113 and the node label from the memory node 114 are read first address about

The signal of the read mark of the simulated branch from the output of the memory node 113 through the pole 44 is fed to the input of the OR element 25 of the control unit 1. If a single label was read, a high level signal is generated at the output of the OR 25 element, which through pole 55 enters the information input of the memory nodes 113 of all branch models 97 of the block 3 branch models. At the considered moment, a high signal is generated at the output of the delay element 32 of the control unit 1.

Whose level of the first pulse of the accelerated series GIZ, which arrived at the input of the delay element 32 from the output of the delay element 31. The delayed signal arrives at the input of the node 15 elements AND, to another input of which the code of the found free branch model is received from the output of the register 10. Formed at the node output 15 elements And the code of the free branch model through the pole 50 is fed to the input of the decoder 120 recording node 98 search for branch models of the block 3 branch models. At the output of the decoder, which corresponds to the number of the free branch model, a high level signal is generated, which enters the recording input of the memory nodes 113 and 114 of the specified branch model. A single label is written to the node FROM the memory of tags of the simulated branches. If the zero mark is read from the node 113 of the memory of the spent branch model, a low level will be present at the first input of the OR 26 block of the control 1, and the output of the element will be The presence of a signal at the second input, which is associated with the output of the comparison node 13. A high level signal at the output of the comparison circuit 13 is generated in the case when the code of the node 9 forming the address of the modeling marks will be equal to the code of the number branch being prepared for modeling coming from pole 35, i.e., when branch number 1 is prepared for modeling. In this case, the high level signal from the output of the OR 25 element goes to the information input of the memory nodes 113 of all branch models 97 via pole 55 block 3 models of branches, and a single label is written to the memory node 113 of the found free model of the branch. Otherwise, a zero mark is written to the memory node 113 of the found free branch model. In this way, a free branch model of the label of the simulated branches at the first address is formed and written into the memory node 113.

Consider how the node label is generated and written into the memory node 114 of the found free branch model at the first address. The signal read from the node label from the output of the memory node 114 of the spent model of the branch of the block 3 models of branches through pole 43

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is fed to the input of the element OR 28 of the control unit 1. If a single mark has been read, a high level signal is generated at the output of the OR element 28. Otherwise, the output signal of the element OR 28 will be determined by the second input of the element associated with the output of the comparison circuit 14. A high level output signal of the comparison circuit is formed when the code of the node 8 forming the address of the modeling marks is equal to the code of the starting node number the prepared branch coming from the pole 41, i.e. if a branch is prepared for modeling with the number of the initial node equal to 1. Thus, a single label signal of the node at the output of the OR element 28 is generated if a single label or a single label is read from the node 114 of the label labels memory of the exhausted model branch. if a branch is prepared for simulation 5, whose initial node is 1. From the output of the OR 28 element, the signal of a single or zero mark via pole 56 is fed to the information input of the memory nodes 114 of all branch models 97 of the block of branch models. As noted, at the time in question, the input from the recording of the memory node 114 of the free branch model receives a signal from the corresponding output of the decoder of the recording 120 of the branch model search 98 98. The label is written to the memory node 114 of the free branch model at the first address.

The next GIZ series signal, which arrives at the counting input of the node 8, which forms the address of the modeling marks of the control block 1 from the output of the OR 26 element, sets code 2 at the output of the node. This code passes through the OR 23 element and the pole 52 to the address input of the tag memory node 113 simulated branches and node 114 of memory labels of nodes of all models of branches 97 of block 3 models of branches. In addition, the GIZ series signal from the output of the OR element 26 of the control unit 1 through the delay element 31 and the OR element 27 enters the input of the node 16 AND elements, to another input of which the code of the spent branch model is received from the output of the register 9. From the output of the node. 16 elements And the code of the spent branch model via pole 5 goes to

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the input of the decoder 121 read the tags node 98 search models of branches of the block 3 models of branches. On the output of the decoder, which corresponds to the number of the branch model that has been fulfilled, a signal will be generated that enters the input of the node 113 of the memory of tags of the simulated branches and the node 114 of the labels of nodes of the specified model of branch 97. The label of the modeled branch from the output of memory 113 via the pole 44 is fed to the input of the OR element 25 of the control unit 1, and the node label from the output of the memory node 114 of the block of 3 models of branches across the pole 43 is fed to the input of the OR element 28 of the control unit I. If a single label is read from the memory node 113 of the spent model of the branch of the block of 3 models of the branches, or the branch number 2 is prepared for modeling, a high level signal is generated at the output of the OR element 25 of the control unit 1, which through the pole 55 enters the information input of the memory nodes FROM all models of branches 97 blocks 3 models of branches. If from the memory node 114 spent my

Deli branch block h models of branches SCHI-JQ element And 19 on the counting input of node 8.

A single tag, or a branch is prepared for modeling, in which the initial node is 2, a high level signal is generated at the output of the OR element 28 of the control unit 1, which through the pole 56 enters the information input of the memory nodes 114 of all branch models 97 of block 3 models of branches.

At the considered moment, in the control unit 1, the second pulse of the GIZ series delayed by delay elements 31 and 32 is generated. This signal is fed to the input of the node 15 elements And, to the other input of which from the output of the register 10 enters the code of the free branch model. From the output of the node 15 elements And the code of the free model of the branch through the pole 50 enters the input of the decoder 120 of the recording of the marks of the node 98 of the search for models of branches of the block 3 models of branches. At the output of the decoder, which corresponds to the number of the free branch model, a signal is generated that is fed to the recording input of the memory nodes 113 and 114 of the specified branch model. There is a recording of the label of the simulated branches from pole 55 into the memory node 1) 3 and the label of the nodes in

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memory node 114 from pole 56 at the second address.

The next pulse of the GIZ series received at the counting input of the node 8 for generating the address of the modeling marks of the control unit 1 sets the output of the node code 3. The described process of forming the label of the simulated branches and writing it to the memory of the free model 113 of the branch 97 of the branch model 3 is repeated , forming a node label and writing it to the memory node 114 of the free branch model at the third address, etc.

The described process of forming the labels of the simulated branches and node labels will continue until the output of the node 8 overflow generates the address of the modeling marks of the control unit 1 a high level signal, which corresponds to sorting through the entire set of possible branch and node numbers. The overflow signal arrives at the zero input of the trigger 12, setting it to the zero state. The zero state of trigger 12 prohibits the passage of GIZ series signals through

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In addition, the overflow signal from the output of node 8 enters its zero input, resetting node 8 to the zero state. This completes the preparation for the simulation of the first branch, leaving the completed node.

The preparatory process begins for the modeling of the second branch on the list leaving the completed site. As noted above, the code of the number of the first output branch from the output of the register 72 of the topology shaping unit 2 arrives at the address input of the node 70 of the memory of the numbers of the output branches. A GI2 signal from the output of the AND 94 element is input to the readout of the indicated node. A memory cell is read from the node 70 at the address of the number of the first branch leaving, the number of the second branch leaving the completed node is read. The code of the number of the read branch from the output of the memory node 70 through the node 86 of the elements OR is fed to the information input of the register 72 and is written into it by a pulse of the GI1 series fed to the setup input of the register from the output of the K 93 element. From the output of the register 72 the code of the number of the second output branches

again arrives at the address input of the memory node 70, as well as through the output pole 35 into the control unit 1

In addition, in block 2 of the formation of the topology, the code of the number of the second output branch from the output of the memory node 70 through nodes 86 and 88 of the OR elements is fed to the address input of the node 69 of the memory of the numbers of end nodes of the network branches o To the read input of the specified node through the OR element 90, a delayed signal of the pulse GI2 is received from the output of the delay element 85. This signal from the memory node 69 reads the code of the number of the end node of the second output branch. The read code from the output of the memory node 69 enters the information input of the register 74 and is written into it by the second pulse GI1 arriving at the setup input of the register from the output of the element 93. From the output of the register 74, the code of the number of the end node of the second output branch goes through polos 34 to control unit 1.

Thus, in preparation for modeling the second outgoing branch, in block 1 of control, block 2 of the formation of topology, via pole 35, follows the code of the number of the branch being prepared, via pole 34 — the code of the number of the end node of the branch being prepared, and through pole 41 is the code of the starting node of the prepared one branches. In addition, the control unit 1, via pole 36, of the topology generation unit, receives the signal of the second pulse GI2 of searching for a free branch model. In block 1 of the control, the search signal for the free branch model from the pole 36 through the OR element 27 is fed to the input of the node 16 elements AND, to another input of which the code of the used branch model is received from the output of the register 9. The formed branch model 16 output And the code of the spent branch model through The pole 51 is fed to the input of the decoder 121 read the labels of the node 98 of the search for models of branches of the block 3 models of branches. At the output of the decoder, which corresponds to the number of the spent branch model, a signal is generated that arrives at the read input of the memory nodes 113 and 114 of the specified branch model. There is a reading of the node label from the memory node 114 at the address of the number of the end node being prepared for the simulator

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the branch arriving from the pole of the control unit 1 through the elements AND 18 and OR 23 and pole 52 to the address input of the memory nodes 113 and 114 of all models of branches 97 of the block 3 branch models. If a single label is read from the memory node 114, meaning that this branch forms a private network loop, the single label signal from the output of the memory node 114 through pole 43 and the control unit element 29 enters the input of element 21, prohibiting the search signal from passing through branch models through this item. In this case, if permitting signals are present at the input poles 37 and 42 (as discussed above), the search signal for the free branch model is formed at the output of element 22. At the output of element 22, and in the case of reading the zero label of the node from the output of element AND 21, the search signal of a free model through the element OR 24 and pole 54 enters the block 3 models of branches. In the latter, a free branch model is searched for by this signal, in the shaper-99 time intervals of which the code of the length of the branch being prepared for modeling is entered. Next, the labels of the simulated branches are formed and recorded in the memory node 113 of the free branch model, as well as the formation of the node labels and their recording in the memory node 114 of the specified branch model. As a result, single labels will be formed in the memory node 113 at the addresses at which single labels were read from the branch 113 memory node and at the number of the branch being prepared for modeling. In the memory node 114 of the free branch model, single labels were read from the memory node 114 of the spent branch model, as well as at the address of the starting node number of the branch being prepared for modeling. This is the way in which preparations are made for modeling the second branch coming out of the completed node.

The described process of preparing for modeling the branches leaving the completed node will continue until the last branch from the list of leaving branches is prepared. After that, at the address of its number in the node 70 of the memory of the numbers of the outgoing branches of the topology shaping unit 2, the code X will be read, signifying the end of the list of outgoing branches. This code is written to the register 72, the output of which is connected to the X state decoder 78. In the decoder, by comparing the codes, a signal is generated at the end of the list of branches exiting the node. This signal from the output of the decoder 78 is fed to the zero input of the trigger 77, setting it to the zero state. The zero state of the trigger prohibits the passage of GI1 and GI2 pulses through AND 93 and 94, respectively. In addition, the interrupt search signal from the output of the decoder 78 through the pole 38 enters the control unit 1 "

In the control unit 1, the interrupt search signal from the pole 38 arrives at the single input of the trigger 11, sets it to the single state, and also through the pole-39 to the block 3 of the branch models. From pole 39, the interrupt search signal is fed to the gate input of the U6 formers of all branch models 97 and to the input of the OR element 118 of the branch model search 98. At the output of the reset generator 116, the model of the branch, to the reset input of the reset generator, which received a signal from the output of the AND 103 element, i.e. the spent branch model, the interruption from which was processed last, will generate a signal arriving at the zero input of the same driver, at the zero input of the busy trigger 100 and at the installation input of the counter 115 nodes. The trigger 100 is set to the zero state, which means releasing this model for further calculations, and to the counter 115

the nodes, the code is recorded, and constantly the second input of the element 106 is input.

given at the poles 64 and which is less than the number of network nodes per unit. The pre-search signal, which arrived at the input of the OR element 118 of the branch model search node 98, will generate a high-level signal at the output. This signal through the pole (1, 1) enters the inputs of the elements AND 102 (1) and 103 (About the first model of branch 97. Since the trigger 101 interrupts the first model of the branch is in the zero state (even if the branch model also worked interval, the interruption from it has already been worked out), on you50

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the resolving potential from the trigger output, and the measuring series pulses from the output of the element 106 are fed to the counting input of the shaper of 99 time intervals, the shapers work on subtraction, and with the arrival of a number of pulses equal to the code recorded in the shaper counter, the latter is zeroed, producing at the output overflow signal. The signals from the outputs of the formers 99 time intervals of the models of the branches 97 arrive at the input of the element OR 118 of the node 98 of the search for models of the branches. Starts0

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During the element 102, a high level signal is generated, which through the pole (2.1) enters the inputs of the elements 102 and (2) and 103 (2) of the second model of branch 97 (2). If the trigger 101 2 of the interrupt of the second model of branch 97 (2) is in the zero state, the signal from the output of the element AND 102 (2 of the second model of branch 97 (2 through the pole (3.1) goes to the inputs of the elements AND 102 (3) | and 103 ( 3) the third model 97 (3), and so on. If at the moment in question in block 3 of the branch models there are still models that have finished modeling the branch durations and the interrupt trigger of which is in one state, the interrupt signal from the output of the And 103 element is the first of such a model through the element OR 119 and the pole 46 enters the control unit 1, where Trigger 11 begins and the process of processing the interrupt from the next branch model begins. If at the time in question there are no models in block 3 of the branch models that have completed the simulation, the interrupt signal is not generated in the block and the potential is present at the output pole 46 low level 3 The low level potential from pole 46 confirms the single state of trigger 11 of control unit 1 and the pulses of the measuring series begin to flow through AND 20 to the input of node 7 of the path measurement and the black without pole 53 in block 3 models of branches.

In block 3 models of branches, the pulses of the measuring series from pole 53 arrive at the input of elements AND 106 of all models of branches 97. For those models of branches that have; trigger 100 is in a single state (the model is engaged in simulating the duration of a branch), on

the resolving potential from the trigger output, and the measuring series pulses from the output of the element 106 are fed to the counting input of the shaper of 99 time intervals, the shapers work on subtraction, and with the arrival of a number of pulses equal to the code recorded in the shaper counter, the latter is zeroed, producing at the output overflow signal. The signals from the outputs of the formers 99 time intervals of the models of the branches 97 arrive at the input of the element OR 118 of the node 98 of the search for models of the branches. The described process of searching and processing interrupts from models that have completed modeling the duration of network branches,

Described processes of preparing outgoing branches for modeling with checking the node label and forming an array of labels of the simulated branches and node labels (building a route of the traced path contour), temporal modeling of the duration of the loaded branches with forming the total path size and processing the interrupt after the simulation of the duration of each branch networks will be executed in the specified sequence. These processes will continue until during the processing of the next interruption it turns out that the end node of the completed branch is not equal to the initial node of the network simulation (the desired path contour has been found). In this case, in the register 75 of the final node of the analyzed branch of the topology shaping unit 2 and in the register 76 of the network node there will be identical codes, and a high level signal will be generated at the output of the code comparison node 8. From the output of node 80, the signal arrives at the input of element 95, to the other input of which the delayed analysis of the completion of the branch of the branch 48 arrives at the output of element 95 and produces a result release signal, which through pole 40 enters the input Node 17 elements AND block 1 control. To the other input of the node 17 elements I receives the code of the magnitude of the path from the output of the node 7 measuring the path. From the output, the node 17 elements And the code value of the shortest path enters the output pole 67.

To determine the branch numbers that make up the shortest path, it is necessary to send high-level single signals to the input pole 57. At the same time, the first signal from pole 57, having passed through the OR 26 element, sets the code of node 8 to 1. This code through the node 23 elements OR and pole 52 enters the address input of node 113 of the memory of marks of simulated networks of all models of branches 97 of block 3 models of branches. In addition, the signal from pole 57 through the element OR 26, the delay element 31 and the element OR 27

arrives at the input of node 1b of elements I. To another input of the indicated node from the output of register 9, the code of the spent branch model arrives, i.e. that branch model, the interruption from which was worked out last. From the output of the node 16 elements And the code of the spent model of the branch through the pole 51 enters the input of the decoder 12 readings of the marks of the node 98 of the search for models of branches of the block 3 models of branches. At the output of the decoder, which corresponds to the number of the branch model,

5, a signal is generated that is fed to the input of the node 113 of the memory of tags of the simulated branches of the specified model of branch 97. A tag is read from the memory node 113

0 at the correct address. If a single label is read from memory node 113, meaning that branch number 1 enters the shortest path loop, a high level signal from the output of the node pa

5 m from FROM through the pole 44 enters the output pole of 65 labels of the branches of the path of the device. The output pole of the 66 numbers of the branches of the paths of the device receives the code 1 from the output of the node 9 block

O 1 control. If, however, a zero mark is read from the node 113 of the block 3 of the branch models, a low level potential will be present at the output pole 65 of the device. This means that branch number 1 is not included in the shortest path contour.

The next impulse from the input pole 57 of the device will set at the input of the node 8 of the control block I code 2, and

0, the process of reading the tag of the simulated branches is repeated for the second address. Single labels at all possible addresses of the network branch numbers will indicate the full path of the shortest path that passes through all network nodes. In the proposed device, the receipt of the necessary preset signals is provided (in Figs., 2 and 3, not shown).

Claims (1)

Invention Formula A network device comprising a control unit, a network modeling unit, a synchronization unit and a topology generation unit, the start input of which is the device start input, the input of specifying the branch number originating from the initial network node of the device connected to the same name of the topology shaping unit , outputs of the branch being prepared for modeling, search for a free branch model, a sign of the final branch of the network, search for an interrupt, and resolution of the result of which is connected to the same input. The control unit's outputs, the outputs of the branch duration code, the clock and search for the free model of the branch of which are connected to the same inputs of the network modeling unit, the outputs of the model number of the branch and the interruption of which are connected to the same inputs of the control unit, the outputs of the number of the completed branch and the beginning of the analysis of the completion of which connected to the same inputs of the topology shaping unit; the interrupt search output of which is connected to the same input of the network modeling block; the first output of the synchronization block is connected to the first clock input of the topology shaping unit, the second output of the synchronization block is connected to the second clock input of the topology shaping unit and to the first clock input of the control unit, the output of the weight of the path of which is the device of the same name, in order to expand the functionality of the device by solving the task of the commie, the outputs of the number of the end node of the branch h of the number of the initial node of the aetvi of the topology shaping unit are connected to the same inputs of the control unit, the output Writing node modeling labels, reading node modeling labels, node modeling labels addresses, a branch modeling attribute and a node modeling attribute of which are connected to the same inputs of the network modeling block, last download network resolution enable outputs, node modeling labels and the modeling labels of the branch are connected to the same names the inputs of the control unit, the outputs of the attribute of the branches of the shortest path of the commie and the sign of the affiliation of the branches to the set of paths of the commutator are homonymous outlets device, specify the number of input nodes in the network which is the same name input of the network simulation and the third sync block output is connected to a second clock input of the control unit, which is a polling input eponymous input device.