SU1282151A1 - Device for determining characteristics of networks - Google Patents

Abstract

The invention relates to the field of computing technology, in particular, to information processing devices of special purpose from the point of view of the design of a computing device. The aim of the invention is to improve the speed in determining the characteristics of networks. The goal is achieved due to the additional input of an operation block containing a block of memory of numbers of occurring events at nodes, a subtractor, registers, elements AND, OR, NOT and delay elements, register of the number of the final network node, a zero state decoder, code comparison block switch, triggers, memory block of the number of branches entering the nodes, two characteristics calculation blocks containing two memory blocks of early endings of events at the nodes, adder, registers and elements AND, OR, memory block of weights codes duration j branches. Two switches are introduced into the topology modeling unit, the initial network node number register and the delay element. The speed in calculating network characteristics is increased by at least 1.5-2 times in comparison with the known devices by changing the procedures for processing the initial information. 3 il. (L from to 00 rsD SP

Description

The invention relates to computing, in particular, to devices for processing information. Special purpose and can be used in the construction of specialized computing devices for modeling network problems of operational management.

The purpose of the invention is to increase the

.strode action device when defined

1 network characteristics.

FIG. 1 shows a block diagram of the device, FIG. 2 is a diagram of a topology modeling unit; in fig. 3 - block diagram of the calculation of characteristics.

The device contains an operation unit 1, a unit 2 for modeling the topology, a unit 3 for calculating characteristics, a generator of 4 clock pulses.

The input of the device is the 5 pole of the signal. Start of the block 2 of the topology simulation. The first, second, third and quarter output poles 6-9 of the 4-clock generator are connected to the corresponding inputs of the operation unit 1 and the topology modeling unit 2. The control output of the operation unit 1 is connected to the input pole 10 of the topology modeling unit 2. The corresponding outputs of the topology simulation unit 2 are connected to the input poles 11-16 of the operation unit 1. The outputs of the operational unit 1 are connected to the input poles 17-19 of the topology modeling unit 2 and to the pole 20 of the characteristics calculation unit 3. The corresponding outputs of the topology modeling unit 2 are connected to the input poles 21-29 of the characteristics calculation unit 3. The output of the characteristic calculation unit 3 is connected to the output pole 30 of the device, which is its information output.

In the device (Fig. 1), the operation unit 1 is intended for organizing a network modeling process. The topology modeling unit 2 is designed to determine the sets of branches exiting from the nodes and their end nodes as well as to generate the corresponding signals and codes necessary for the operation of other units of the device. Characterization calculation unit 3 is designed to determine, store and calculate the calculated characteristics of the simulated network. Generator

4 clock pulses is designed to synchronize the work of all blocks of the device. The first, second, third, and fourth outputs of the generator 4 clock pulses, connected to its output poles 6–9, are intended for supplying to the respective inputs of the blocks of the device shifted relative to each other a series of clock pulses, respectively, ГИ1, ГИ2, ГИЗ and ГИ4.

Operational unit 1 (Fig. 1) will contain block 31 of memory of event numbers in nodes, block 32 of memory of the number of branches included in nodes, subtracter 33, three registers 34-36, register 37 of the number of the final network node, decoder 38 zero state, block 39 comparison of codes, two switches 40.41, first 42, second 43 triggers, eight elements AND 44-51, third trigger 52, element OR 53, element NO 54, four elements 55-58 of delay.

The topology modeling unit 2 (Fig. 2) contains a block 59 of memory of numbers of branches leaving branches, a block 60 of memory of numbers of first branches leaving branches, a block 61 of memory of numbers of end nodes of branches, a register 62 of the starting network node, a register 63 output branch numbers, 64 state decoder, two switches 65 and 66, two triggers 67 and 68, four AND 69-72 elements, two OR 73 and 74 elements, a delay element 75;

In block 2 of modeling the topology, block 59 of the memory of numbers of branches leaving branches of nodes is intended for storing lists of branches numbers leaving branches of the simulated network. Block

The 60s of the numbers of the first branches leaving the nodes are intended for storing the numbers of the first branches of the lists of the branches leaving the nodes. Block

The 61 of the end node node numbers are intended for storing the terminal node numbers of all the branches of the simulated network. Register 62 of the starting node number is intended to store the code of the starting node number of the network to be configured. Register 63 of outgoing branch numbers is intended for recording, storing and issuing codes of branch numbers leaving the network nodes. A state decoder 64 is intended for decoding X code. Switches 65 and 66 are designed

31

for separating in time two data streams arriving at the same input.

The block 3 for calculating the characteristics (FIG. 3) contains the block 76 of memory of the early events at the nodes, block 77 of the memory of the codes of the branch length, adder 78, three registers comparison circuit 82, switch 83, group 84, element 85, element OR 86,

In block 3, characterization of block 76 of the memory of early endings of events at the nodes is intended for recording, storing and issuing intermediate and final codes of the values of the early endings of the events of each network node. The block 77 of memory codes of the lengths of the branches is intended for storing the initial data on the magnitudes of the durations of all the branches of the network. Code comparison circuit 82 is designed to compare two codes and form an output signal when there is a code on the second input that is larger than the first one. The group of elements And 84 is intended for submission to the information output of the device of the N-bit result code. All other triggers, elements AND, OR, NOT, the elements of delays in the device are intended to organize the correct operation of the circuit and prevent races.

The device is intended to determine the magnitude of the longest path and other characteristics of the networks. These characteristics include the values of the early beginnings and the early endings of the branches, the early achievements of the nodes, the free reserves of all the branches of the network.

The early completion of any node corresponds to the length of the longest path to this node from the initial network node. Thus, the device determines the magnitudes of the longest paths from the starting node to each node of the network under investigation.

The characteristics of the network branches: early start, early finish, and free reserve are determined by the outcome of early achievements of their starting and ending nodes. The magnitude of the early onset of the branches coincides with the magnitude of the early end of their initial node, the magnitudes of the early end of the branches are defined as the sum of their early beginnings and their durations, and the free reserves

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51 .4 as the difference between the values of the early achievements of their end nodes and the early endings of these branches.

The optimal and functionally complete set of source data for obtaining any of the listed network characteristics is the set of values of the longest paths from the initial to each node of the network and the set of values of the lengths of the network branches. Since the second component of this set is present as the source data in the same way as the topological information about the network under study, the task is to obtain a set of values of the longest paths from the initial to each network node.

The device works in the following way.

Preliminary, the numbers of the first branches leaving the initial nodes 60, the numbers of the branches leaving the initial nodes 59, and the numbers of the ending nodes of the branches 61 of the topology modeling unit 2 of the topology modeling network are entered into the memory blocks. In memory block 59, information is entered in the form of lists of branches leaving the network nodes, i.e. at the address of the previous branch of the list going out from the node by the vetei, the number of the subsequent is recorded, and at the address of the last the code set X is recorded. The numbers of the first lists are stored in memory block 60 by the addresses of the numbers of the lists that are initial In memory block 61, the branch addresses contain the numbers of their end nodes. Such a set of topological information is sufficient for the device to work by defining a given set of characteristics. The register 62 stores the number of the initial network node,

In memory block 77 of block 3 for calculating characteristics, the duration codes are entered by the addresses of the branches, and the code of the number of branches included in this node is pre-recorded in memory block 32 of the operation unit 1. In the register 37 of the operation unit 1, the code of the number of the end node of the network is entered. The remaining all registers and memory nodes of the device are pre-cleared, and the triggers are zeroed.

.

5128

After performing the described presets and entering the listed initial information, the device begins to work on the Start signal, which comes from the input pole 5 of the device to the block 2, which is then flat. The Start signal, through the OR 74 element, sets up the control trigger 67 and, via the OR 73 element, sets the trigger 68 and enters the read input of the block 60 of the memory of the first branches leaving the nodes, Since the trigger 42 of the operation unit 1 is in the zero state, then through pole 10 a control signal of the switch 65 enters the zero signal which allows the input of the block 60 of the starting node number from the register output 62 of the initial node through the switch 66 to the address input of the switch 60

As a result, the Start-up signal at the output of memory block 60 reads the number of the first branch that is coming out of this node, which through switch 66, controlled by the single state of trigger 68, goes to

register information entry 63. Od

Newly from the switch output code

The starting node numbers go through pole 23 to characterization calculation unit 3 and through switch 83, which is controlled by a single signal coming through pole 24 from flip-flop 68, to the address input of block 76 of the memory of early endings of events in the nodes. The output signal of the element OR 73 of the topology simulation unit 2 is through pole 26 and the element OR 86 is fed to the read input of the same memory block 76. At the output of memory block 76, a zero code is read corresponding to the value of the early execution of the initial network node event. The early event code of the node enters the information input of the register 80, where it is recorded by the Start signal delayed by element 75. delay of the topology simulation unit 2, and received at the input of the resolution recording of the register 80 of the performance calculator via pole 21,

The trigger 67 of the control unit 2 modeling the topology, set in a single state by the Start signal, allows the formation of control pulses at the outputs of the And 69-72 evil signals.

15

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5 20

thirty

 , 55, e-

40

45

sixteen

synchronous pulses GI1-GI4 clock generator arriving at the inputs of these elements, respectively, through the poles 6-9.

By a pulse GI1 from the output of the element AND 69, the code of the number of the first branch starting from the start node is written into the register 63, from the output of which the number of the end nodes of the branches in the memory of the end branch of the first branch is read to the address input of the memory 61 block 61. leaving the start node. The code of the branch number from the output of the register 63 through the pole 29 is fed to the address input of the memory block 77 of the durations of the branches of the block 3 for calculation of characteristics. In the memory block 61, the code of the number of the end node of the branch in question passes through pole 16 to operation unit 1 to the address input of memory block 32 of the number of branches entering the nodes and through pole 22 enters the second input of switch 83 of characteristic calculation 3.

The pulse GI2 from the output of the element 70 in the block 59 of memory of numbers of branches leaving branches is read to the address of the number of the first branch, the code of which number from the output of register 63 goes to the address input of block 59 of memory, the code of the number of the next output from this ( initial) node of the branch. On the same signal, the trigger 68 is set to the zero state. In the memory block 59, the code for the number of the next branch goes to the second input of the switch 66, now controlled by the zero signal of the trigger 68, and from its output goes to the information input of the register 63. The zero signal from the output of the trigger 68 through pole.24 allows The arrival of the code of the number of the end node of the first output branch, the code of which is still in register 63, through the switch 83 to the address input of the memory block 76 of early events at the nodes of the performance calculation block 3. The control pulse from the output of the element AND 70 of the modeling unit 2 of the topology is via pole 27 and the element OR 86 is fed to the input of the hell of the block 76 of the memory of the block 3 for the calculation of characteristics. By the number of the end node of the branch, the value of the early completion of this node is read.

The code of the read value is fed to the information input of the register 79. At the same time, the same signal from pole 27 in the block 77 of the memory of the scales of the lengths of the branches reads the code of the length of the branch considered in register 63. The read code of the duration of the branch arrives at the information input of the register 81 of the block 3 calculating the Ta characteristics. At the same time, the pulse from element 70 through POLUS 15 is fed to the read input of block 32 of the memory of the number of branches of the operational block entering the nodes, 1, where it reads the written code that goes to the first input of the subtractor 33, the second input of which The subtractor 33 reduces by one the value of the number of branches included in the node recorded in memory block 32. The code of the resulting difference will allow the writing of a new code, which

It goes to the information input of register 34, where it is recorded by the same control impulse, which is delayed for a corresponding time by delay element 55 and fed from its output to the write enable input of register 34. From the output of register 34, the new code of the number of branches entering the node goes to the information input of the block 32 memory coli30

From the output of the adder 78, it enters the information input of the memory node 76, at the next clock cycle GI4 in control. The first signal sent from element I 72 through pole 25. Thus, in block 76 of memory at the node number address, the maximum value of the early termination from the i-considered branches entering the given node will be recorded. When will all be considered

the number of branches included in the node, as well as 35 branches entering the node, is written to the input of the decoder 38, where, compared to the number of this node, the value is autonomous with the code zero. If the code received early in the register 34 is zero, then the execution of this node. If the code is

the output of the adder 78 does not exceed the code in register 79, then the output of the comparison circuit 82 will be a zero signal, which

This means that all members of the node

patches are reviewed and the node is committed. Then the output of the decoder 38 produces a single signal that will allow the formation of control pulses at the outputs of the AND 44 and 45 elements. If the code in register 34 is not zero, then the output of the decoder will have a zero signal.

The clock pulse GIZ from the output of the element And 71 through the pole 28 will record the existing code of the early fulfillment of the end node of the branch in question in the register 79 and the code of the duration of this branch in the register 81 of the characteristics calculation unit 3. The output of register 80, in which the code for the early completion of the initial node of the branch in question is stored by this moment, and the register register 81 are connected to

40

50

will not allow the new value to be written, and in memory block 76 by node number, the old value will be preserved. still the largest of all previously reviewed.

As already discussed, the GI2 clock signal in the register 34 of the operation unit 1 is entered by decreasing by one the code of the number of branches included in the final node of the analysis-. branch being developed. The resulting code from the output of register 34 goes to the information input of memory block 32 of the number of branches included in the nodes, where it is recorded at the address of the number of the end node of the branch being analyzed.

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five

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inputs of adder 78, the output of which will result in a code of the value of the early termination of a given branch, which may be equal to the value of the coefficient of the early completion of the end node of the branch if it is the maximum among all the branches entering this node. To verify this, the resulting code from the output of adder 78 goes to one of the inputs of comparison circuit 82, to another input which receives the code from the output of register 79, in which the code of the early completion of this node is written, equal to the maximum of the codes of the early terminations considered previously entered into this node branches or equal to zero, if such branches have not yet been considered.

If the code received at the output of the adder 78 is greater than that available in register 79, then at the output of the comparison circuit 82 a single signal is received, which, having entered the input of the element And 85,

0

From the output of the adder 78, it enters the information input of the memory node 76, at the next clock cycle GI4 in control. The first signal sent from element I 72 through pole 25. Thus, in block 76 of memory at the node number address, the maximum value of the early termination from the i-considered branches entering the given node will be recorded. When will all be considered

40

0

will not allow the new value to be written, and in memory block 76 by node number, the old value will be preserved. still the largest of all previously reviewed.

As already discussed, the GI2 clock signal in the register 34 of the operation unit 1 is entered by decreasing by one the code of the number of branches included in the final node of the analysis-. branch being developed. The resulting code from the output of register 34 goes to the information input of memory block 32 of the number of branches included in the nodes, where it is recorded at the address of the number of the end node of the branch being analyzed.

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15

which comes through the pole 16 from the output of the block 61 of the memory of the end nodes of the branches of the block 2 of the topology simulation. A recording signal is generated at the output of the element 71 of the topology modeling unit 2 synchronously with the clock of the low-frequency laser and through the pole 13 enters the recording input of the block 32 of the memory of the number of branches of the operational unit 1 entering the nodes.

If the code formed in register 34 is greater than zero, then this means that not all the branches included in this node have been analyzed and then, using clock pulse GI4, operation unit 1 does not perform any actions, since the zero sirnal at the output of the decoder 38 the zero state is blocked by the formation of the control signal of the output signals of the element 45. In this case, only the described operations are performed on the block 3 for the calculation of the characteristics of the clock pulse.

If the code obtained in register 34 is equal to zero, then this means that all branches included in this node have been analyzed, i.e. the values of their durations are taken into account in the block for calculating the characteristics and, therefore, their end node has been completed. The completion of a node implies a transition to the analysis of the branches emerging from the initial (or any other) node, therefore, the number of the completed node must be remembered. Since during the current analysis of the outgoing branches a certain number of nodes may be accomplished, it is necessary to organize a certain order of storing the numbers of such nodes. 40

The numbers of the accomplished nodes are recorded as lists in the memory block 31 of the numbers of the occurring events in the nodes. This process is organized by the sletopologiya through the switch 40 of the operation unit 1, the code of the number of the end node of the branch being analyzed. In this case, the switch 40 is controlled by a single signal coming from the single input of the trigger 67 of the block 2 of the topology simulation via a pole pole 14. The information of the memory block receives the contents of the register 35 and the input of the higher (n + 1) -th the input bit is the signal from the inversion output of the trigger-52. In the initial state, the trigger 52 is in the zero state, and the register 35 is cleared. When a signal is received from the decoder 38 about the completion of the first network node, the signal from element AND 44 is stored in memory block 31 according to the number of the completed node, register 20 is stored and 35 is one in most (n + 1) -th bit, which is mark the end of the list.

A control signal, a synchronous GI4, coming from the topology modeling unit 2, via pole 12, sends a signal to the output of the AND unit of the operational unit 45, which also produces a control signal at the output of the And unit.

30 The control signal from the AND element 45 is fed to the resolution input of the register 35, the information input of which receives the code of the number of the completed node. This code is written to register 35, and the trigger 52 with the same control signal is set to one. As a result, by the end of the clock signal GI4, register 35 stores the number of the first completed node, and in memory block 31 at the address of the number of this node in the (n + 1) th high-order bit, the end of the list is recorded. In the course of the ongoing analysis

25

35

blowing way. Zero code in register-45 outgoing branches of the next CEO node

five

0

the topology through the switch 40 of the operation unit 1 enters the code of the number of the end node of the analyzed branch. In this case, the switch 40 is controlled by a single signal coming from the single input of the trigger 67 of the block 2 of the topology simulation via a pole pole 14. The information of the memory block receives the contents of the register 35 and the input of the higher (n + 1) -th the input bit is the signal from the inversion output of the trigger-52. In the initial state, the trigger 52 is in the zero state, and the register 35 is cleared. When a signal is received from the decoder 38 about the completion of the first network node, the signal from the AND 44 element in the memory block 31 according to the number of the completed node records the contents of the register 35 and one to the most significant (n + 1) -th bit that is labeled end of list.

A control signal, a synchronous GI4, coming from the topology modeling unit 2, via pole 12, sends a signal to the output of the AND unit of the operational unit 45, which also produces a control signal at the output of the And unit.

30 The control signal from the AND element 45 is fed to the resolution input of the register 35, the information input of which receives the code of the number of the completed node. This code is written to register 35, and the trigger 52 with the same control signal is set to one. As a result, by the end of the clock signal GI4, register 35 stores the number of the first completed node, and in memory block 31 at the address of the number of this node in the (n + 1) th high-order bit, the end of the list is recorded. In the course of the ongoing analysis

five

five

re 34 is converted by the decoder 38, the zero state to a single signal at its output, which has arrived at the inputs of the elements And 44 and 45, allows

one .,., , - .

forming on their heads. control signal.; By the control signal from pole 13 from topology modeling unit 2, a signal is generated at the output of element 44, which is the number of this node through pole 16 to the input of switch 40, which is still controlled by a single signal with poles 14, and after 50 switch 40, to the address input of memory block 31.

On the control signal, synchronous GIZ, from the AND element 44 of the operation unit to the memory unit at

steps into the recording entry block 31 memory -55; the numbers of the new accomplished node of the numbers of accomplished branches. The number of the previous superconnecting input of this memory block is written from the pole 16 of the simulation unit 2, which was wired during this analysis. the outgoing branches of the node stored

The number of this node, via pole 16, goes to the input of switch 40, which is still controlled by a single signal from pole 14, and after 50, switch 40 to the address input of memory block 31.

On the control signal, synchronous GIZ, from the AND element 44 of the operation unit to the memory unit at

111

in the register 35. In the higher (n + 1) -th bit of the same information word, the label is absent, since the trigger 52 is already in the unit state - the scientific research institute and the zero signal is supplied to the input of the (n + 1) -th bit the clock signal GI4 at the output of the element 45 forms a control signal, which records the code of the number of the newly completed node in register 35 and confirms the single state of the trigger 52. As a result, by the end of the clock signal GI4, the number 35 of the last signal network node, and in block 31 of memory by address The number of the subsequent network node that is stored contains the code of the number of the previous network node. At the address of the number of the first node made. The mark is written in the (n + 1) th discharge. When receiving a signal from the decoder 38 about the completion of the next node, the described operations are repeated.

The analysis of the branches leaving the initial node of the network ends at a signal received via pole 11 from block 2 of the topology modeling. This signal is generated by the decoder 64, which defines the next code in register 63 of the exiting branches as X code, which is a sign of the end of the list of branches leaving the starting node. The signal from the output of the decoder 64 sets the trigger 67 to the zero state and stops the operation of the unit 2 for modeling the topology by analyzing the branches leaving the node. This completes the stage of analyzing the branches leaving the initial network node. Thereafter, the device proceeds to the analysis of the branches emerging from the catch that occurred during the previous step. Since the entire set of nodes has been written down as a list in the memory block 31 of the numbers of the completed nodes of the operation block 1, it is necessary to analyze the branches leaving each node of this list, and only after that go to the analysis of the branches leaving from the newly completed nodes, which will also be recorded in the memory block 31 of the operating unit as a new list.

By the signal from pole 11 from the topology modeling unit 2, the trigger 42 of the operational unit 1 is set to one. Trigger 43

15112

The processing labels in the initial state are in the zero state and, successively, only at the output of the element I 49, a control signal will be generated from the clock signal of the GIZ, which will set the trigger 52 of the label to the zero state and through the element 53 will enter the input register register resolution 36. The information input of this register through the switch 41, which is currently controlled by the zero signal of the processing label trigger 43, will receive the contents of register 35, which currently contains the code of the node number that is cial svershivshihs in the list of nodes n schihs church in the block memory 31. The code of the number of this node will be written to register 36 on the clock of the GIZ. Then the same control signal, delayed for a certain time, having passed through the delay element 58, will set the trigger 43 of the processing marks to one state. Then (already on the clock signal GI4) at the output of the element And 48 a control signal will be generated which will arrive through pole 18 into l block 2 of the topology modeling and perform almost all the functions performed by the Start signal.

Exceptions will be as follows. The node number in the topology simulation unit 2 comes from the output of the register 36 of the operating unit 1 through pole 17. From the pole 17, the node number code goes to the second input of the switch 65, which is currently controlled by a single signal from the pole 10, where it comes from the single output trigger 42 operating unit. Consequently, the output of the switch 65 is not the contents of the register 62 of the starting node number of the network, but the code of the number of the completed node recorded in register 36 of operational unit 1. The trigger 67 of the topology modeling unit 2 is set to one with a signal from pole 19, where it comes from output element And 51 operating unit. So, to the inputs of the AND 51 element, a control signal of the GI 4 delayed by the delay element 57 is received from the AND 48 element and an inverse signal from the code comparison block 39, which generates a signal in case of a code of the completed node in register 36

13

when the end node of the network in the register 37, then at the output of the element 51 and the pole 19, the signal is somewhat lighter than at the pole 18, and only if the node whose analysis of the outgoing branches is to be done is not the terminal node of the network.

At the same time, the signal from the output of the delay element 57 resets the trigger 42 to the zero state and stops the operation of the operation unit 1. Next, the described operations of the analysis phase of the branches leaving the node are repeated. No differences, except noted, from the above description.-No. Only at the end of the stage, due to the fact that all this time the trigger 43 of the processing label was in the single state, an output signal will be generated at the output of the E 46. At the clock signal G112, the feedback signal will be generated, the address input through the switch 40, which currently controls the zero signal from 14 (since the trigger 67 of the topology modeling unit 2, after completing the stage, analyzing the list of branches leaving the node, is reset to zero) being in register 36. By this address Su from the memory unit 31 will be read the next code in the analyzed sniske svershivshegos node.

The read code from the output of the memory block 31 through the switch 41, controlled by a single signal from the flip-flop 43, is fed to the information input of the register 36 and is recorded there by the clock signal of the GIZ from the output of the And 47 element. If the readout code is the number of the completed node of the analyzed list, then the output of the highest (n + 1) --th bit will again contain a zero mark signal, which will prohibit the formation of a signal at the output of the element 50. If in (n + 1) - m If de is a unit, it means the end of processing of this list of accomplished nodes and at the output of the element I 50, a signal is generated which, through the delay element 56, flushes the trigger 43 of the processing marks to the zero state. Then the clock signal GI, formed at the output of the element And 48, the signal is not

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will be generated, and only after a clock cycle again on the clock signal of the GIZ, the signal at the output of the element 49 will begin, which will begin the described stage of analysis of the completed nodes of the new list, the initial code of which will be in register 35.

Such a sequence for analyzing the lists of completed nodes and the branches exiting from them will be executed until the last list consisting of the end node of the network is formed and analyzed. What will be on the list

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25

thirty

35

40

Only one element is obvious, since the subsequent lists are formed on the basis of the previous ones, and to complete the end node of the network it is necessary to roll out all its nodes, since the device simulates connected oriented networks with one initial and one end nodes.

When analyzing this last list, the end node of the network will be entered into register 36 and then, at the output of the code comparison block 39, a single signal is produced that results from the coincidence of the codes in registers 36 and 37 which, through the HE element 54 and the AND 51 element, will prohibit the control flow signal through pole 19 and block 2 modeling topology. As a result, it will not be included in the analysis of the branches emerging from this node (since they are absent), and in block 3 of the calculation of characteristics from the output of block 39, a signal will be sent through pole 20 to issue a code for the longest path in the network which is 45

It sews through a group of elements 84 and outputting the contents of register 80 to the output pole, where the signal from pole 21 will read the code for the early completion of this node, which, by definition, corresponds to the length of the longest path.

By this time, information about the magnitudes of early events of all network nodes, i.e. codes of the longest paths to each node (from the initial). In conjunction with the initial information about the values of the activities of the branches in memory tree 77, this will make up a functionally complete set of initial data for quickly determining any of the listed sets to calculate 50

15 12

myh characteristics, as well as their any composition. The use of new blocks (operational and calculation of characteristics) allows, in contrast to the known devices, to significantly reduce the calculation time and to refuse to use the block of vertical channel models.

When modeling a network, there is no process of temporal modeling of branch durations, and when estimating the node convolution, a block of 32 bits of the number of branches included in the nodes is used. This leads to the fact that the process of analyzing the completion of the node is significantly reduced, since it is not necessary, after completing each branch entering the node, to go through the entire list of incoming branches, checking the completion of each. It is enough to check the number of unfulfilled branches, which, as a code, are constantly generated and corrected in memory block 32.

Claims (1)

Invention Formula A device for determining network characteristics, comprising a clock pulse generator, a topology modeling unit comprising a memory block of numbers of branches emerging from nodes of branches a memory of numbers of end nodes of branches, a memory block of numbers of first branches leaving branches, a state decoder, two triggers, four AND elements and two OR elements, with the device start input connected to the first inputs of the first and second OR elements, the outputs of which are connected respectively to the single inputs of the first O and the second trigger, a single input of the first trigger is connected to the first inputs of the first and second elements, the second inputs of which are connected to the first and second outputs of the clock generator, the output of the first element AND is connected to the read input of the memory of numbers of end nodes of the branches and to the input permitting the write of the register of numbers of output branches, the output of the second element SH is connected to the read input of the memory block of the numbers of the first output branches of the branches, the output of the second element I is connected to the reading hole of the memory block and nome five 0 five 0 five 0 five 0 five 15116 A ditch of branches going out of nodes and with zero input of the second trigger; the output of the register of numbers of output branches is connected to the address inputs of the memory block of the numbers of branches leaving branches and the numbers of end nodes of the branches and the state decoder input, the output of which is connected to the zero input of the first trigger, characterized in that, in order to improve speed, a topology modeling block includes two switches, a register of the starting network node number and a delay element, an operational block containing a memory block of numbers events in the nodes, the block of memory of the number of branches entering the nodes, the subtractor, three registers, the register of the terminal node number, the zero state decoder, the code comparison unit, two switches, three triggers, eight AND elements, the OR element, the NOT element, a delay element and a parameter calculation block containing an early event event block in the nodes, a block of weights for the duration of branches, adder, three / registers, a comparison circuit, a switch, a group of AND elements, an AND element and an OR element, and a register input number on The initial node of the topology modeling block is the first information input of the device a, the output of the register register of the initial node of the network of the topology simulation block is connected to the first information input of the first switch of the topology modeling block, the control input of which is connected to the single output of the first trigger of the operational block, single output the second trigger of the topology modeling unit is connected to the control input of the second switch of the topology modeling unit, the output of which is connected to the information input of the outgoing branch numbers register, the first and second information inputs of the second switch of the topology modeling unit are connected respectively to the outputs of the memory blocks of the numbers of the first branches out of the nodes and the numbers of the topology block outlets from the nodes, the first inputs of the third and fourth elements and the topology modeling unit are connected to the single output of the first trigger, a tolology modeling unit — the second inputs of the third and fourth elements AND the topology modeling unit are connected respectively to the third and fourth outputs of the clock generator, the output of the third element And the tolology modeling unit is connected to the terminal input of the first And element and to the recording input the block of memory of the number of branches of the operating unit entering the nodes, the output of which is connected to the first input of the subtractor of the operating unit, the second input of which is connected to the source of a standing single signal The outputs are connected to the information input of the first register of the operating unit, the output of which is connected to the information block of the memory of the number of branches of the oleration block entering the nodes, whose address input is connected to the information input of the second register of the operational block and with the output of the memory block of the numbers of end nodes of the branches of the topology simulation block, the output of the fourth element AND the topology modeling block is connected to the first input of the second element a AND operation unit, the output of the second element AND topology modeling unit is connected to the read input of the memory block; the input is ac1X to the branch nodes and the input of the first delay element of the operating unit; the output is connected to the write enable input of the first register of the operating unit whose output is connected to the input the zero state decoder of the operation unit, the output of which is connected to the second inputs of the first and second elements AND of the operation unit, the output of the first element AND of the operation unit is connected to the input Records of the memory block of the numbers of events that occurred in the nodes of the operational block, the outputs of the lower bits of which are connected to the corresponding information inputs of the second switch of the operational block, the control input of which is connected to the single output of the second trigger of the operational block and to the first inputs of the third fourth and fifth elements And the operating unit, null: - oh output of the second trigger operation O 0 0 The first unit is connected to the first input of the sixth element AND of the operational unit, the output of which is connected to the input of the second delay element of the operational unit and the output of the second delay element of the operational unit is connected to the zero input of the first trigger of the operating unit; the output of the state decoder of the topology block is connected to the single input of the first the trigger of the operating unit, the unit output of which is connected to the second inputs of the third, fourth, fifth and sixth elements AND the operating unit, the third in rows of the third, fourth and fifth elements and the operation unit are connected respectively to the second, third and chetvertm outputs clock generator, the third input element of the sixth AND operation unit connected to the third output of the clock generator impul5 0 owls, the output of the second element And opera0 The operation unit is connected to the unit input of the third trigger of the operation unit and with the output resolution of the recording of the second register of the operation unit, the output of which is connected to the second information input of the second switch of the operation unit and with the lower bits of the information input of the memory block of numbers of events input (n + 1) The 5th bit of the information input of which is connected to the zero output of the third trigger of the operation unit, the output of the second switch of the operation unit is connected to the information input of the third register of the operation unit, the output of which is connected to the second information input of the first Kot iMyTaTopa operating unit and the second information input of the first switch of the modeling unit topology, the control input of the first switch of the operating unit is connected to a single input of the first trigger of the topo modeling unit logia, the output of the first switch of the operating unit is connected to the address input of the memory block of the numbers of events in the nodes of the operating unit, the output of the third element 55 And the operating unit is connected to the input-read block of memory of numbers of events in the nodes of the operational block, the output of (n + 1) -th 0 whose bit is connected to the first input of the seventh element AND an operation unit, the second input of which is connected to the first input of the first element OR the operational unit and to the output of the fourth element AND the operational unit, the output of the seventh element And the operational unit is connected to the input of the third delay element of the operational unit, output which is connected to the zero input of the second trigger of the operation unit, the output of the fifth element AND the operation unit is connected to the second input of the second element OR of the topo model the logic and input of the fourth delay element of the operation unit, the output of which is connected to the single input of the second trigger of the operation unit and the first input of the eighth element AND of the operation unit, the second input of which is connected to the output of the element NOT of the operation unit, the input of which is connected to the output of the operation code comparison unit , the output of the eighth element AND the operating unit is connected to the second input of the first element OR of the topology modeling unit, the output of the sixth element And the operational unit is connected to the left input of the third trigger of the operation unit and to the second input of the first element OR of the operation unit, the output of which is connected to the recording enable input of the third register of the operation unit, the output of which is connected to the first input of the code comparison unit of the operation unit, the second input of which is connected to the output of the final number register the network node of the operational block, whose input is the second information input of the device, the output of the block compared to the codes of the operational block is connected to the first, second inputs of the AND elements groups of the characteristics calculation block whose second inputs are connected to the outputs of the first register of the characteristics calculation block, the output of the second OR element of the topology modeling block is connected to the first input of the OR element of the characteristics calculation block and the input of the delay element of the topology modeling block whose output is connected to the recording enable input of the first register block calculation of characteristics, the output of which is connected to O 0 five the first input of the adder of the performance calculator, whose output is connected to the information input of the memory of early events in the nodes of the performance calculator, whose output is connected to the information inputs of the first and second registers of the performance calculator, the output of the memory of the numbers of end nodes of the branches is connected to the first information input of the switch of the characteristics calculation unit, the second information input of which is connected to the code of the first switch of the modeling unit of the topology and the address the input of the memory block of the numbers of the first branches of the topology modeling block leaving nodes, the single output of the second trigger of the modeling block of the topology is connected to the control input of the switch of the performance calculator, the output of which is connected to the address input of the memory block of early endings of events at the nodes of the performance calculator, the output of the fourth element And the topology modeling unit is connected to the first input of the element AND of the characteristic calculation unit, the output of which is connected to the recording input of the early window memory block events in the uz- , lakh of the characteristic calculation unit, the read input of which is connected to the output of the IL element of the calculation unit, and 5 characteristics, the second input of which is connected to the output of the second element AND topology modeling unit and to the read input of the memory block of the scales of the length of the branches of the characteristic calculation unit, the output of which connected to the information input of the third register of the performance calculation block, the output of which is connected to the second input of the adder of the performance calculation block whose output is connected to the first input of the comparison circuit the block of characteristics calculation, the output of the third element AND the topology modeling block is connected to the recording resolution inputs of the second and third registers of the characteristics calculation block, the output of the second register of the characteristics calculation block is connected to the second input of the comparison circuit of the characteristics calculation block whose output is connected to the second input of the element And the block of calculation is characteristic, the output of the register of numbers is 0 0 five 0 21128215122 The moving branches of the topology block of the COO elements and the group of the block are distributed with the address input of the memory block of the characteristics, the intimates of the length of the branches of the block are formational codes of the device and the calculation of the characteristics, and the outputs are all. phage. / Editor S. Pekar F1 / G3 Compiled by S. Nazarov Tehred M. Khodanich Proofreader E. Syrohman