SU1273941A1 - Device for patitioning graphs into subgraphs - Google Patents

Abstract

The invention relates to the field of computer technology and can be used for the automated solution of the electronic circuit layout problem. The aim of the invention is to simplify the device. This goal is achieved by introducing a group of elements AND, a group into the control unit. counters, OR elements, delay elements and a ban element, and each channel of the random combination generator consists of a source of a Poisson pulse stream, an AND element, a ban element, an OR element, a trigger, and a 2H-IiIBi element. 1 hp f-ly, 4 ill.

Description

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CD 4; ib The invention relates to computing and can be used in an automated solution to the task of arranging electronic circuits. The purpose of the invention is to simplify the device. FIG. 1 shows a block diagram of the device; in fig. 2-4 - possible variants of functional schemes of a random combination generator, a combination converter - a code and a control unit The device contains a register 1 of the combination code lock, a generator of 2 random combinations, a graph topology display unit 3, a buffer register 4 of the display, a control block 5, a converter 6 combinations of code , register 7 code of the remainder of the edges, subtractor 8, comparison circuit 9, register 10 of the code of the number of external edges, block 11 of the display registers, input 12 of the initial state setup and input 13 of the topology of the initial graph. Each channel of the generator 2 (Fig. 2) consists of the source 14 of the Poisson pulse stream, element 15, prohibition element 16, element 17, trigger 18 and element 2I-I1TI 19o converter combination - code (Fig. 3 shows a diagram of the converter five inputs) contains ten two-input elements OR 20 and 21, which form four rulers and are connected in a corresponding way, the nepBjrio ruler includes four elements OR 20 and 21, the second - three elements OR 20 and 21, the third - two elements OR 20 and 21 and the fourth - one element OR 20 and 21 "In addition, the pre The former 6 contains a combinational circuit consisting of prohibition elements 22-25 and the elements OR 26 and 27. The control unit 5 (FIG. 4) contains the element OR 28, the group of elements AND 29, the group of counters 30, the element OR 31, the counters 32 and 33, de-decoder 34, serially connected delay elements 35-38, OR elements 39, 40, delay element 41, elements OR 42, delay elements 43, 44, AND element 45, prohibition element 46, OR element 47, trigger 48 and outputs 49 -55. The essence and principle of operation of the proposed device are as follows. 2 The partition of the graph G (X, U) consisting of (x | n and vertices and | Ul V edges, into subgraphs G, - (X (, and,), G - (XJ, and), ..., Gg (Xj, Uj) with the number of vertices in each subgraph, respectively jxj n, n, .. lXj | Tij, where n, + Pg +, oo., + Go to n for each stage. random assignments n | verpgin in the i-th subgraph. The number of random assignments Q (lotteries) is determined by the given accuracy and reliability of the division of the graph into subgraphs, and all parallels in each assignment are selected simultaneously (in parallel). the number of external connections, Toe. the number of connections between the vertices selected in the subgraph and all remaining ones (not selected in any subgraph). If the result of the current random assignment is a version of the subgraph with a smaller number of external connections than in the previous assignment, then it is remembered. Thus, the i-th subgraph formed after the i-th stage has a locally-minimal number of external links. The vertices included in the i-th subgraph are blocked and excluded from the further drawing. Thus, in the first stage, Q random assignments are made; n, the vertices in the first subgraph. The number of external links is counted after each random assignment between the selected set of vertices X X (hereinafter, the sign above the corresponding letter means not the final, but the current set) and the remaining vertices,. After all the Q random assignments have been made, a second subgraph G (X, U, U) is formed, having a locally minimal number of links with the remaining set of vertices. At the second stage, the second subgraph is formed by performing the next series of Q random assignments. In this case, n vertices are chosen randomly from the set remaining after the first stage, the vertices, and the number of external links is determined after each random assignment between the selected set of vertices X (and the remaining set vertices X (X,. UXj,). After all the Q random assignments have been completed, the second

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the subgraph G (X, U), which has a locally minimal number of external links with the remaining set of vertices X (X, and X,). Similarly, the subgraph formation process continues until the last 1st stage, after which the remaining set of vertices X (1JX,) is included in the ith subgraph. Since at each stage a subgraph is formed with a locally minimal number of external links, the total number of links between subgraphs is also locally minimal. In the proposed device, the topology of the original graph is defined using block 3 of the graph topology mapping. Random selection of a given number of vertices is carried out using a generator of 2 random combinations. Using register 1 of the combination code lock, subgraphs formed in the previous steps are blocked. In register 4 of indication, the option of forming a subgraph (number of vertices), the best relative to the previous options, is entered. Converter 6 converts various combinations of single signals at its inputs to the corresponding binary code at the outputs. The code corresponds to the number of edges between the vertices, to which, in block 3 of the graph topology mapping, single signals are fed. Register 7 is designed to store during each stage of the formation of subgraphs of the code of the remainder of the edges incident to the vertices that are not included in this stage in any of the subgraphs. Using the subtractor 8, the number of external links is calculated. After each random assignment, Comparison Unit 9 compares the number of external communications resulting from this assignment with the number of external communications obtained from the best variant of all previous random assignments. The buffer register 10 is entered after comparing the best current number of external links. The display unit 11 is designed to visualize the numbers of the vertices of each subgraph after the optimal partitioning of the original graph. The control unit 5 sets the number of subgraphs, the number of vertices in each subgraph and the number of random assignments, as well as all control signals are generated.

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The device is prepared for operation by setting the initial topology of the graph to block 3 displaying the graph topology by supplying single signals to the corresponding inputs 13, setting the capacities of the counters 30, corresponding to the dimensions of the subgraphs being formed, the capacity of the counter 32 corresponding to the number of assignments 10 and the capacity of the counter 33 corresponding to given number of subgraphs.

The operation of the device (Fig. 1) begins with the supply to the input 12 of a setup signal of the initial state. By

5, the signal 1 sets the register 1, the triggers 18 in the generator 2, the registers of the display unit 11, the counters 30, 32, 33 and the trigger 48 in the control unit 5, the register 20 is set to one. In addition, single signals are sent to all inputs of block 3 by the same signal, therefore register 7 records the total number of edges connecting all vertices of the original graph. After that, in the generator of 2 random combinations, random combinations begin to form, i.e. on a given number of its outputs,

0 but in a random combination, single signals appear. It happens as follows. At the outputs of the sources 14 pulses (Fig. 2) at random times generate pulses with time intervals between which satisfy the Poisson flow. The random impulse that occurred at the output of any of the sources 14 passes through the corresponding E51 element 15 and the prohibition element 16 to one of the triggers 18. Since the output of each element 5 and is connected to the direct input of its prohibition element 16 and to the inverse inputs of all

5 foreign elements of the prohibition, the random impulse that occurred at the output of any of the sources 14, the first prohibits the passage of random impulses with

0 other sources 14 through all other elements of the 16 ban. This prevents the fusion of several pulses at the outputs of the inhibit elements into one at the output of the element OR 28.

5 At the forward output of that trigger 18, to which a random impulse passed, a single potential appears, and the zero potential from its inverted output closes the corresponding element 15. This ensures that only 15 impulses per period are passed through the elements 15 and the prohibition elements forming one random combination. Random pulses from the outputs of the prohibition elements 16 simultaneously arrive at the control unit 5 at the inputs of the OR element 28 (Fig. 4). "At the same time, they first pass through the first (upper according to the scheme) AND element Rupp 29 to the first counter group 30, as a unit with the zero potential output of the decoder 34 is open and it is this element group 29. After the first counter 30 to the number of random pulses supplied equal to its capacity, the first blend is formed. The first counter is reset, and the signal from its output through the OR element 31 is fed to the inputs of the counter 32, the first delay element 35, the OR element 39 and the single trigger input 48. The zero signal from the inverse trigger output 48 blocks all AND elements 15 what is needed to prevent random impulses from passing through these elements during computational operations c. other blocks of the device. At the same time, a pulse from the output of the element OR 39 appears at the output 50 and enters the lower elements of AND 19, thereby connecting the direct outputs of the flip-flops 18 to the inputs of block 3. As a result, single signals are sent to the elements corresponding to the vertices of the graph , and at the outputs of block 3, displaying the edges of the graph, incident to those elements of the vertices, on which single signals are applied, the same signals appear. To obtain information about the number of connections (i.e., the number of outputs of block 3, on which single signals appeared), the number of outputs with single signals, arranged in an arbitrary order, is necessary, converted into binary code. This is accomplished with the aid of the converter 6. FIG. 3 shows an example of the implementation of the converter-55.

five inputs and, respectively, three outputs, since the number in the range from O to 5 is represented by 3

register 10. In view of the fact that the maximum code was first written into register 10, then after the first case there was a 3-bit binary code. In this converter, a pyramid scheme of pairs of elements AND, OR 20, 2 compands the output signal, i.e., any combination of units at the inputs converts into the same number of units, but located next to the next outputs of the pyramid scheme, starting from the top output. FIG. 3 shows an example of the arrival at the inputs of the converter 6 of three single signals to the second, fourth and fifth inputs, respectively. At the output of the pyramid scheme, single signals appear on the first, second and third inputs. Next, the compressed pyramidal signal is converted by a combinational circuit consisting of prohibition elements 22-25 in a binary code of the number of edges incident to the excited vertices. The code goes to the subtractor 8. and the second time-generating signal from output 51 of block 5, subtracts from the code of the total number of edges of the original graph recorded in register 7 with the signal for setting the initial state. As a result, in the reader B, the number of edges representing the sum of the outer edges of the selected subgraph after the first assignment, and all internal edges connecting the remaining vertices, i.e. vertices not allocated to a subgraph. To obtain only external edges from the resulting number, you must subtract the number of edges connecting the remaining vertices. This is accomplished by connecting the third in time pulse occurrence generated by the output 52 of unit 5. In this case, a single signal from output 52 is fed to the input of generator 2, i.e. all the upper inputs of elements 2I-W. 19. Then the fourth single signal (and the second at output 51) is fed to the subtractor 8 from the output 51 of block 5, resulting in the number of external edges of the selected subgraph in the subtractor 8 after the first random assignment. After that, the comparison circuit 9 from the output 49 of the block 5 receives the fifth impulse of formation time, according to which the codes of the subtractor 8 and the buffer

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tea assignment, it is always greater than the code of the number of external edges of the subtractor 8. Therefore, the comparison circuit 9 generates a signal (this signal is sixth left), which is used to rewrite the code from the subtractor 8 to the register 10. The same signal goes to the input the buffer register 4 of the display, and through the OR element 48 of the block 5 - to the input 50 of the generator 2. As a result, the direct outputs of the flip-flops 19 are connected to the register 4 and the first variant of the generated first subgraph is written to it.

Then, the seventh pulse generated at the output of the delay element 43, through the elements OR 17, resets the triggers 18 and through the prohibition elements 46 and OR 47 the trigger 48 to the initial state. At the same time, all elements of AND 15 are opened and the entire device is ready for the formation of a new random assignment. Similarly to the one specified in generator 2, a second random assignment is formed, in subtractor 8 the number of external edges between the second variant of the first subgraph and all remaining vertices is determined, and comparison scheme 9 determines from two variants of the first subgraph that variant which has a smaller number of external edges. If it turns out that the first version of the first subgraph is better, then the comparison circuit 9 does not produce a signal at its output, and the same information remains in register 4 and register 10 (in register 4, the number of vertices of the first version of the subgraph, and in register 10, the number of its external edges). If the second variant of the subgraph turns out to be better, then a signal is produced at the output of the comparison circuit 9, as a result of which the numbers of the vertices of the second variant of the first subgraph are rewritten to register 4 from generator 2, and the number of its external edges from subtractor 8 to register 10. This continues until generator 2 generates a predetermined number of assignments. Then, a single signal appears at the output of the counter 32, which opens the element AND 45 and closes the prohibition element 46 and, after a time specified by the delay element 41, appears at its input. The delay is needed in order to

its assignment managed to be processed in accordance with the specified sequence of control pulses from the first to the seventh five. The signal from the output of the delay element 41 goes to the control inputs of registers 1, 7 of registers of block 11 and through the element OR 42 to the inputs of upper elements AND 19. At the same time, beam 0 The first variant of the first subgraph (i.e., the numbers of the corresponding vertices) from buffer register 4 is written into the first register of the display register unit 11, since the enable signal

5, the decoder 34 enters the first register of block 11 and the combination code lock register 1, so the corresponding outputs of register 1 are in the zero state, and the initial maximum code is written to register 20 of the master 10.

Since by this time all the flip-flops 18 are set to a single signal from the output of the delay element 43 to the initial state (all the inverse outputs of the flip-flops 18 have single signals), the generator 3 is connected to the generator 2 or the reverse outputs of the register 1 (Fig. 2).

0 Therefore, in block 3, those are excited

the outputs that correspond to the edges connecting the vertices that are not in the first subgraph. Converter 6 converts the number of excited outputs to a binary code, and it is written to register 7.

The signal from the output of delay element 41, staying on delay element 44, writes a unit to counter 33, with the result that a single signal appears at the second output of decoder 34 and opens for receiving information the second counter 30, This signal from the output of delay element 44 through the open element AND 45 (at the output of the counter 32 a single signal is still valid) and the element OR 47 sets the trigger 48 to the initial (zero) state, which unlocks the elements AND 15. After that, the whole device is ready to form the second subgraph.

Similarly, the best variant of the second subgraph is formed and

Claims (1)

5, the numbers of its vertices are recorded in the second register of the display unit 11, and in register I, the numbers of the vertices of the second subgraph are added to the register numbers of the vertices of the first subgraph. Accordingly, the number of inverse outputs of register 1 is reduced, on which single potentials remain, i.e. the number of vertices not included in any of the subgraphs is reduced. The third subgraph is already formed from these remaining vertices, etc. until all subgraphs have been formed. A sign of the end of subgraph formation is the appearance of a signal at the output of counter 33. Claim 1: Apparatus for dividing a graph into subgraphs containing a combination code lock register, random combination generator, the first group of control inputs of which are connected to inverse outputs of the code lock register combinations, graph topology mapping unit, edge residual code register, converter combination - code whose inputs are connected to the graph topology mapping unit goders, subtracter, circuit compared and, the register register of the number of external edges, whose outputs are connected to the first group of inputs of the comparison circuit, the output of which is connected to the read input of the register of the number of external edges, whose information inputs are connected to the second group of inputs of the comparison circuit and the outputs of the detector, the first group of inputs of the reader, is connected to the outputs of the register of the remainder of the edges, the second group is connected to the outputs of the converter of the combination — the code and the information inputs of the register of the code of the remainder of the edges, the buffer register of the indication, the register block the control unit, including the 1st two counters, the decoder, the inputs of which are connected to the outputs of the second counter, the trigger, the five OR elements, the five delay elements, and the AND element, which, in order to simplify the device, a group of N elements AND (N is the number of graph vertices), a group of N counters, the sixth OR element, the sixth and seventh delay elements and the prohibition element, while the information outputs of the random combination generator are connected to the inputs of the graph topology display unit and information the inputs of the buffer display register, the control outputs of the random combination generator are connected to the inputs of the first element OR, the inputs of the buffer register register are connected to the information inputs of the registers of the display unit and the register of the combination code lock, the output of the first element OR is connected to the first inputs of the elements AND group of the control unit, the second inputs of which are connected to the outputs of the decoder and the inputs for enabling the recording of the registers of the display unit, the outputs of the elements AND of the group of the control unit are connected to the counters and inputs of the corresponding counters of the control unit group, the outputs of which are connected to the inputs of the second OR element, the output of which is connected to the input of the first counter, the input of the first delay element and the first input of the third OR element, the second input of which is connected to the input of the second delay element and connected to the output comparison circuits and the enable input of the recording of the buffer register of indications, the output of the first counter is connected to the input of the third delay element, the first input of the AND element and the inhibiting input of the prohibition element, info Its input is connected to the output of the second delay element, the output of the first delay element is connected to the input of the fourth delay element and the first input of the fourth OR element, the output of the fourth delay element is connected to the input of the fifth delay element and the first input of the fifth OR element, the second input of which is connected with the output of the third and the input of the sixth delay element, the output of which is connected to the input of the second counter and the second input of the element I, the input of the fifth delay element is connected to the input of the seventh element This delay and the second input of the fourth OR element, the outputs of the AND element and the inhibit element are connected respectively to the first and second inputs of the sixth OR element, the output of which is connected to the single trigger input, the zero input of which is connected to the output of the second OR element, the third and fifth outputs S1I elements, the second delay element and the zero output of the trigger of connection 1 1 and the second group of control inputs of the random combination generator, the output of the fourth element Hjrf is connected to the control input of the subtractor, the output ter its delay element is connected to the control inputs of the combination code lock register, the register of the remaining edge code, the external edge number code register and the indication block registers, the output of the seventh delay element is connected to the control input of the comparison circuit, the installation input of the initial state of the device is connected to the third input of the generic OR input and the inputs to zeroing the register of the combination code lock, random combination generator, graph display topology block, edge remap code register, number code register and external ribs per Vågå, second counters and group counters of the control unit, and information display unit inputs the topology graph are information inputs. 2, the device according to claim 1, characterized in that the random combination generator comprises N channels, each of which consists of a source of a Poisson pulse stream, element AND, prohibition element, element OR, trigger and element 2И-Ш1И, the first inputs of elements AND form The first group of control inputs of the random combination generator 4112 SRI, the second inputs of the And elements are connected to the outputs of the sources of the Poisson pulse stream, the outputs of the And channel elements i (i 1, N) are connected to the information inputs of the i-ro channel inhibitors and prohibit the inputs of the restraint elements of the other channels, the outputs of the inhibit elements are connected to the single inputs of the trigger of the corresponding channels and form the control outputs of the random combination, the zero inputs of the trigger of each channel are connected to the outputs of the corresponding OR elements, the first inputs of the 2I-1-SHI elements of each channel are connected to the first inputs of the corresponding And elements, the second and third inputs of the 2I-Sh1I elements of each channel are connected respectively to the zero outputs of the flip-flops and the third inputs of the And and ed elements the triggers of the corresponding channels, the outputs of the 2I-RSHI form information outputs of the random combination generator, combined (by the like elements) fourth inputs of the AND elements, first inputs of the lilMy elements, the third and fourth inputs of the 2I-OR elements form the second group of control inputs of the random combination generator , and the combined second inputs of the OR elements are the setup input to the initial state of the random combination generator. f1 / g7 -i