SU1314335A1 - Device for comparing two numbers - Google Patents

Abstract

The invention relates to computing and can be used in the construction of control equipment for checking the passage of information in discrete devices of various types and for checking the operability of memory devices, counters, registers and other more complex discrete devices. The purpose of the Invention is to increase the speed of a device for comparing numbers. The device contains subtractive counters, groups of elements AND, multiple inputs AND, groups of elements AND-NOT, OR, elements OR-NOT, NOT, I. The set of entered elements and connections allowed after-each tact of subtracting units from the counters to reset those the number bits in which both numbers appeared units, which eliminated the need to supply subtractive pulses in an amount equal to one of the numbers, and, as a result, led to an increase in speed. 1 hp f-ly, 3 ill. to (L: le 00 W) ate

Description

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The invention relates to computing and can be used in the construction of control equipment for checking the passage of information in discrete devices of various types and for checking the operability of memory devices, adders, counters, registers and other more complex discrete devices.

The purpose of the invention is povigeniya speed.

Figure 1-3 shows the block diagram of the proposed device.

The device contains subtractive counters 1, groups of elements AND 2, element NOT 3, element AND 4, multiple inputs AND 5, element 6 delay, elements AND 7, trigger 8, group of elements AND-NOT 9, group of elements OR 10, element AND-NOT 11, element OR - NOT 12, element NOT 13, inputs 14-17, outputs 18-20. Each subtractive counter 1 contains a D-flip-flop 21, elements AND 22, inputs 23-26.

The device works as follows.

Before the device starts operating, the signal Resetting the counters I of the first and second numbers is given to the input 16 of the device, which is fed to the NOT 3 element and to the single input (S input) of the standard RS flip-flop 8 with direct inputs. The signal passing through the HE 3 element is inverted, fed to the common zero reset inputs 24 of the first and second counting subtraction counters 1 and zeroed. The signal arriving at the S input of the RS flip-flop B sets the trigger to one state and a logical O (zero) appears on its inverse output that arrives at AND 7 elements of the first and second numbers and through the AND-NOT element 11, - on the item NOT 13.

Thus, at the outputs 20 of the device of the first and second numbers and at the output 19 of the device after issuing a signal, the zeroing of the counters 1 of the first and second numbers will be, 0.

Next, the inputs 14 of the device are supplied to the first and second compared numbers, which, according to the signal from input 15 from the external control unit, through the blocks of elements I 2 are written to the counters 1 of the first and second numbers.

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The states of direct outputs 27 of counters 1 of the first and second number are connected to the block of I-HE elements 9, from the outputs of which the information enters the inputs 26 of subdivision zeroing of counters 1 of the first and second numbers, while the binary digits of the counters of the same name 1 the first and second numbers containing the logical units (1) are nullified.

The signal from the input 15 is also supplied to the R input of the trigger 8, through the element 6 of the delay. After the trigger 8 is set to O, the inverted output of the trigger 8 produces a single signal that goes to the first and second number AND 7 and the AND-NE element 11 and is the enable signal for issuing information to the outputs 20 of the first and second number and output.

After zeroing of the same-named bits in the counters 1 of the first and second numbers containing 1, if none of the counters 1 has completely zeroed out, the zero signals from the multiple-input elements AND 5 of the first and second numbers are fed to the inputs of the IL-NOT 12 element. its output is generated by a single signal, which permits the passage of sync pulses (SI) to the input 17 of the device from the external control unit, through the element 4 to the subtracting inputs 23 of the counters 1 of the first and second numbers.

After each 1 of the counters 1 of the first and second numbers are subtracted, through the block of the elements AND –NE 9, those bits of the counters 1 of the first and second numbers are zeroed out in which both of them have 1. This happens until one of the counters 1 of the first and the second number is not about

Zeroes completely.

For the sake of clarity, let us consider the algorithm for calculating the error of counters in the following example:

10100011 1 clock cycle - zeroing I 0001111 bits with a common

00100000 00001100

2 tact - subtract 1 from both counters

3131

00010100 3 clock cycle - resetting 00000000 common 1

When zeroing at least one of the counters 1 of the first or second number on its inverse outputs 27 and 28 (their) will be 1, which go respectively to the multi-input element And 5 of the first number and / or to the multi-input element And 5 of the second number, then from outputs to the first and second inputs of the element OR-NOT 12, respectively, generating a zero signal at its output, which is the signal to prohibit the supply of SR through the element 4 to the subtractive inputs 23 of counters 1 of the first and second numbers. This completes the number comparison process.

At the same time, on the block of the device outputs 18 (through the block of the elements OR 10) there will be the result of the number mismatch. For the external control unit, the end of the comparison process will be the presence of at least one of the outputs 20 or output 19. At the output 20 of the first number (via element 7 of the first number, signal 1 will be if only counter 1 of the first number is reset, i.e. the second number is greater than the first, at the output 20 of the second number through the element And 7 of the second number) will be 1 if the counter 1 is reset to the second number, i.e. the first number is more than the second. At output 19 (through the elements AND NOT NOT Pi NOT 13) there will be 1 if the counters 1 of the first and second number are wrapped simultaneously, i.e. if the numbers first and second are equal.

After zeroing the counters I of the first and second numbers and receiving the initial numbers, the operation cycle is repeated.

The trigger 8 is necessary for blocking spurious signals of the device that occur at the outputs 20 of the first and second numbers and output 19, at the moment of the initial zeroing of the counters I of the first and second numbers and recording the initial numbers in them.

The delay element 6 is required to delay the switching of the trigger 8 to O for the time required for bit-by-bit zeroing of the same-bit bits in the compared numbers after they are received in counters I of the first and second numbers.

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The period of the clock pulses supplied to the input 17 of the device must be greater than the response time of the counters I of the first and second

the numbers when subtracting the next 1 plus the time of a bit zeroing of the same-named unit bits of counters 1 of the first and second numbers.

Thus, the possibility of a bit zeroing of the same-named bits of numbers containing 1 makes it possible to significantly increase the speed of the device. Counters 1 of the first and second numbers are identical and

work as follows.

For the general zeroing of the counter 1, it is necessary to apply a zero signal to the input 24 of the general zeroing of the counter 1, which, -access through the elements And 2

on asynchronous R-inputs (4th inputs) of flip-flops 21, sets them to O. To reset zero counter 1, zero signals are applied to double-zero zero counter 1, and then through elements 2 to asynchronous R-inputs of those triggers that need to be reset.

The number to be written to the counter 1 is supplied in binary code to the installation inputs 25 of the counter 1. The direct (first) outputs of the trigger 21 are the direct outputs 27 of the counter 1, and the inverse (second) outputs - the inverse outputs 28

counter 1.

In this counter 1, the state of the K-th bit (K 1, n - 1, where n is the size of the discharge grid) is directly transmitted to the next input (k = bit, which occurs only after switching all previous bits.

With the counting (third) C-input of each subsequent trigger 21 is connected to a single (first) output

trigger 21 neighboring low bit. The trigger 21 of the most significant bit will be transferred only if the trigger 21 of the next least significant bit is transferred from state O to state 1.

Claims (2)

Invention Formula one . A device for comparing two numbers containing a subtracting counter, a multi-input element AND, two groups of elements AND, a trigger, an element NOT, 513 three elements AND, the inputs of the first comparative number of the device are connected to the first inputs of the corresponding elements, the second inputs are connected to the write output of the device AND of the first group, and the outputs are connected to the installation inputs of the detracting counter, the inverse outputs of the bits of which are connected to the inputs of the multi-input element And, the output of which is connected to the first input of the first element AND, the output of which is the output of the Smaller device, and the second input is combined with the first input of the second element AND, the output of which is More device, characterized in that, in order to increase the speed of the device, the second element NOT, the second subtractive counter, the second multiple-input AND element, AND-NOT, OR, AND-NOT, OR delay, moreover, the inputs of the second compared number of the device are connected to the first inputs of the corresponding elements AND of the second group, the second inputs of which are connected to the recording input of the device, and the outputs are connected to the installation inputs of the second subtractive counter, the inverse outputs of which are bits are united with the inputs of the second multiple input element AND, the output of which is connected to the first inputs of the OR-NOT and NAND elements and the second input of the second AND element, the device recording input is additionally connected through the delay element to the installation input to the O trigger, the installation input to 1 which is connected to the device reset input, and through the first element is NOT connected to the reset inputs of the detracting counters, the counting inputs of which are connected to the output of the third element I, the first input of which is connected to the clock input of the device, and the second input chen to the output of the element ILN-NOT, the second input of which is connected to 6 the output of the first multi-input element AND and the second input of the element NAND, whose third input is connected to the inverse output of the trigger, and the second the input of the first and second elements are AND, and the output is connected to the third inputs of the first and second elements AND and the input of the second element NOT whose output is the output Equal to the device, the inputs of the installation in О the bits of the first and second subtractive counters are connected to the outputs of the corresponding elements AND- NOT groups whose first and second inputs are connected to direct outputs of bits, respectively, of the first and second subtractive counters and the first and second inputs of the corresponding OR elements, the outputs of which are the outputs of the device difference. 2. The device according to claim 1, wherein the subtracting counter contains n D-flip-flops and n elements, And the reset input of the subtractive counter is connected to the first inputs of the elements And, the second inputs of which are the installation inputs to O the corresponding bits of the subtracting counter, and the outputs are connected With the installation inputs in O of the corresponding D-flip-flops, the installation inputs in 1 of which are the corresponding installation inputs of the subtractive counter, the information input of each trigger is connected to its inverse output and is the inverse output of the corresponding discharge counter counter, the direct output The 40 D-flip-flop is the direct output of the corresponding bit of the subtracting counter, and the direct output of the K-th D-flip-flop, where K 1, ..., (n - 1), n is the digit number, is connected to 45 synchronous input (K + 1) -th D-flip-flop,. the sync-input of the first D-flip-flop is the counting input of the subtract counter. eleven fia. f s with Yu 7 / -about FIG. g 8 27 23 25 26 28 27 28 27 25 26 24 Editor Y. Sereda Compiled by E.Ivanova Tehred M.Hodanich Order 2214/49 Circulation 673 Subscription BNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-355, Raushsk nab., 4/5 Production and polygraphic enterprise, Uzhgorod, st. Project, 4 Proofreader I.Shulla