SU1309289A1 - Information pulse discriminator - Google Patents

Abstract

The invention relates to various areas of radio electronics. The purpose of the invention is to increase the noise immunity of the selector. The selector contains And 1 ... 3 elements, trigger 7 and delay lines 9 and 10. To achieve this goal, elements AND 4 and 5, trigger 8, elements OR 11 and 6, pulse generator 12, frequency dividers 13 and 14, counters 15 and 16 were introduced into the selector and new functional connections were formed. 2 Il. so about soo oo so (rig.1

Description

The invention relates to times; 1 areas of radio electronics (computing, radar, teleautomatics, etc.), where pulsed sigpaly are used.

The purpose of the invention is to improve noise immunity when the frequency of the clock pulse and the time shift between clock and information pulses changes.

FIG. 1 shows a structural electrical selector circuit of the impulses; in fig. 2 - time diagrams.

The pulse selector contains five elements AND 1-5, the first element OR 6, two triggers 7 and 8, two delay lines 9 and 10, the second element OR 11, the generator 12 pulses, two dividers 13 and 14 frequencies, counters 15 and 16, input 1nin 17 and output tires 18 and 19.

The input bus 17 is connected to the first input of the third element I 3 and the input of the first delay line 9, the output of which is connected to the second input of the third elec- tector I 3. The output terminal is connected to the second inputs of the first 1 and second 2 elec- Both and the reset input of the first trigger 7, the direct and inverse outputs of which are connected respectively to the first input of the first 1 and the inputs of the second 2 and fifth 5 AND elements, the output of the first electric element I being the first output spike and connected to the first input of the element OR 6 and the installation input of the second trig The core 8, the reset input of which is connected to the output of the second element I 2, which is the second output bus, and the first input of the fourth element I 4, the second input of which is connected to the forward output of the second trigger 8, and the output to the second input of the first an OR element (the output of which is connected to the input of the second counter 16 and the second delay line 10, the output of which is connected to the R-input of the nerve counter, whose information outputs are connected to the corresponding information inputs of the second counter 16, whose information outputs dinene with the inputs of the second element OR 11, the output of which is connected to the installation input of the first trigger 7. Moreover, the output of the generator 12 of the pulses is connected to the inputs of the first 13 and second 14 frequency dividers, and the output of the nerve dividers 13 frequency is connected to the second input of the fifth element And 5, the output of which is connected to the subtractive input of the second counter 16, and the output of the second frequency divider is connected to the summing input of the first counter 15.

The pulse selector works as follows.

The signal from the input layer 17 is fed to the first delay line 9 (Fig. 2a), which delays it by a time less than the length of the useful signal pulses - and - clock pulses (TI) and information

impulses, but longer duration of impulse noise (Fig. 26). Then, the delayed signal on the third element And 3 is compared with the non-delayed one. At the output of the third element And 3 a signal is filtered from impulse noise (Fig. 20), which then goes to the first input: iepBoro trigger 7 to the second inputs of the first 1 and second 2 elements I.

In the initial position from the moment iiKi, which occurs after several cycles of the selector aimed at its auto-synchronization, the next TI passes through the first element I 1 to the first output 18 and to the second input of the element OR 6 (Fig. 2 and). From the output of the OR 6 TI element (Fig. 2n), the second delay line 10 arrives and enters the record of the counter 16, according to this signal, the recording is not cut into the counter 16 and the information from the outputs of the counter 15, ime, 1, has the same number of bits, as counter 16 (Fig. 2d). After that, the output of the second delay line 10 of the delayed TI (Fig. 2 o) causes the counter 15 to be reset (Fig. 2 g, time tg). At the same time, the first trigger 7 (Fig. 2e, g), which closes the first element I 1 and opens the second element I 2, through which the next information bus 19 passes the second information bus

(Fig. 2, moment tio), in addition, the nerve trigger 7 opens the fifth element I 5 (Fig. 2 g), through which the output of the first frequency divider 13 to the counter 16 receives a read pulse. At interval Tj, counter 16 is zeroed (Fig. 2e, mon.

t ,,), and at the output of the second element OR 11, a signal is generated, by which the first trigger 7 is reset, at which the second 2 and fifth 5 And elements are closed, and the first And element opens, through which the first output bus passes the next TI (Fig. 2 n, time t, z).

Thus, the counter 15 in each period of the following TI projects the number of i.pulses arriving at its sum.m.r. (Counting) input from the output of the second frequency 14 frequency amplifier.

For a clock pulse, the code value counted in counter 15 is transferred to counter 16, which in the next period of the TI counts it with pulses coming from the output of the nerve divider frequency 13, having a division factor of less than the second divider frequency 14.

In this case, a time interval T is formed on the first trigger 7 (Fig. 2 e, the interval tg - t, j), in which the next information pulse is expected (Fig. 2 b, temp. T, o).

The magnitude of the interval T, in each period of TI, may vary depending on the duration of the preceding period of TI and is equal to

T, J,

where K | - the division ratio of the second frequency divider 14;

Kj is the division factor of the first frequency divider 13; T - previous period of the TI.

The optimal interval T of the information pulse search is formed by selecting the division factors Kg and Ki for the second 14 and first 13 frequency dividers.

For the case (Fig. 2a), when the information pulses are shifted by 0.5T to the clock, the optimum interval T (3/4 T, therefore, the division factors of the second 14 and first 13 frequency dividers are 4/3.

The initial position of the information pulse selector enters automatically after the first information zero (no pulse) appears in the information signal. In the interval t - tucx. The process of auto-synchronizing the information pulse selector is illustrated. In the interval t - ts, due to the lack of information pulses and an arbitrary state of the triggers of the counter 15, at the moment the device is turned on, the first trigger 7 generates an information pulse search interval T (Fig. 2e, g, interval ti -) corresponding to the following period TI equal to 2 Tg, and therefore the second TI (Fig. 2, moment t) falls in the interval T ", which reaches the second information output value 19. When the first information pulse appears (Fig. 2, the moment te) triggers the second trigger 8 (Fig. 2n). At the first input of the fourth element 4, a potential appears that permits the passage of the next pulse (Fig. 2m, moment t) to the second bus 19. This pulse, which is TI, passes through the first input of the element OR 6 (Fig. 2n, time i) to the write inputs of counters 15 and 16. At the same time, the true value of the TI following period is rewritten into counter 16, and counter 15 is zeroed by the delayed TI, and with the arrival of the next TI (Fig. 2, moment 1cg) for the selector comes working mode.

five

0

about 5 5

0

Claims (1)

Invention Formula Information pulse selector containing the first and second delay lines, the first and second output bars, the first, second and third element I, the first trigger, the forward and inverse outputs of which are connected respectively to the first inputs of the first and second element I, the second inputs of which combined with each other, the output of the first element And is the first output, and the first and second inputs of the third element And are connected respectively to the input and output of the first, the first delay, and the output from the reset input of the first trigger, distinguishing Qc in that, in order to increase the noise immunity as the frequency and the sequencer clock. time shift between clock and information pulses, the second trigger, the fourth and fifth element AND, the first and second element OR, the pulse generator, the first and second frequency divider, the first and second counter, and the setting input of the second trigger are connected to the output The first element AND and the first input of the first element OR, and the input input with the output of the second element AND, which is the second output length, and the first input of the fourth element I, the second input of which is connected to the right output of the second trig - gera, and the output with the second input of the first OR element, the output of which is connected to the recording input of the second counter, and the input of the second delay line, the output of which is connected to the R input of the first counter, whose information outputs are connected to the corresponding information inputs of the second counter, information outputs which is connected to the inputs of the second element OR, the output of which is connected to the installation input of the first trigger, the inverse output of which is connected to the first input of the fifth element L, and the output of the pulse generator with It is connected to the inputs of the first and second frequency dividers, and the output of the first frequency splitter is connected to the second input of the fifth And element, the output of which is connected to the subtractive input of the second counter, and the output of the second frequency divider to the summing input of the first counter, and the output of the third element And connected to the second input of the first element I. Information FIG. Z L to / 7/2 out