SU1307452A2 - Polyfunctional logic module - Google Patents

Abstract

The invention relates to automation and computing technology and is intended to implement logical functions of two variables depending on the training signals with the ability to confirm the health in the process of functioning as intended. The invention is an improvement of the invention according to the author. St. No. 915073. The purpose of the invention is to improve the testability of the module. The multifunctional logic module contains four elements NOT 9, 10, 16, 17, four elements AND II, 12, 13, 19, element ZI-2ShSh 17, three elements UNIMAL 21-23, element IS-NOT 24, elements OR 14, 15 , 25, two information inputs, two configuration inputs, five outputs. The module has the ability, when operating at certain input effects or when testing it with these input effects, to reveal constant faults of any of its elements. This improves the testability of the module and shortens the time needed to troubleshoot both the elements of the module and the modules themselves used to build various discrete devices. 1 pc., 2 tabl. with CO

Description

The invention relates to automation and computing and can be applied in building reliable self-monitoring systems.

The purpose of the invention is to improve the controllability of the multifunctional log module during operation.

The drawing shows a diagram of the multifunctional logic module

The device contains information inputs 1 and 2, configuration inputs 3 and 4, outputs 5-8, elements NOT 9 and 10 elements AND 11 - 13, elements OR 14 and 15, element NOT 16, element ZI-21 SHI 17, element NOT 18 , Element AND 19 ,, Element OR 20, Elements NEGATIVE 21 - 23, Element NO 24, Element OR 25 and Control Output 26.

The principle of operation of the multifunctional logic module is described in Table 1.

Consider the work of the proposed module, for example, at the next input set, and training signals,. In this case, in accordance with the expressions describing the information outputs of the module 5 - 8., logical signals,, and are formed on them. This is evidenced by the fact that at these values of the input and training signals, signal 1 is generated only at the input of the element And 13, on the remaining elements And 11 and 12 there is an O signal, which causes the indicated output.

At the same time, the specified input and tuning signals arrive at the elements NOT 16 and 18, element I 19 and element ZI-2ILI 17, forming the signal O at the output of element ZI-2IPI 17 and signal 1 at the output of element I 19, which, in turn causes a signal 1 at the output of the element OR 20, which is fed to the second input of the element UNEMATCH 23. The first input of the element UNIMQUAL 23 also receives the signal J from the information output of module 7, which determines the presence of the O signal at the output of the UNEQUALITY 23 element. Signal O is present at the output element AND NOT 24, since its inputs receive signals generated by the elements UNEQUAL. CHARACTER 21 and 22. Thus, with an intact pa6oj e module for control

five

five

0

five

g s

0

At output 26, signal O is present. If one of the faults of type constant 1 occurs on informational inputs 5 and 8, the module or constant O on any of the elements HE 10 and I 13 and information outputs 6 and 7 of the module at control output 26 for a given set of inputs and The training signals generate a signal 1, which signals the presence of a fault in the multifunction logic module. Table 2 shows the diagnostic dictionary with which you can determine the malfunction of the multifunctional logic module.

The proposed multifunctional logic module realizes all the logical functions of two variables and at the same time has a significant advantage — the ability to self-control in the process of functioning. The use of the module in building various digital devices allows us to simplify the diagnosis of the module itself, as well as significantly improve the control and maintainability of digital devices and shorten the time for troubleshooting.

Claims (1)

Invention Formula Multifunctional logic module auth.St. N 915073, which means that, for the purpose of verifying testability, two NOT elements, the AND element, two OR elements, the AND-NOT element, the ZI-2IL element, and three NOTABILITY elements, and the first information the input of the module is connected to the input of the third element NOT, the output of which is connected to the first input of the fourth element I, the second input of which is connected to the second information input of the module and the input of the fourth element NOT, the output of which is connected to the first input of the first element I of the element ZI-2IL, second input which with It is one with the first configuration input of the module, the first information input of which is connected to the third input of the first element AND ZI-2IL element and the first input of the second element AND ZI-2IL element, the second input of which is connected to the second information input of the module, the second configuration input of which is connected with the third input of the second element And the ZI-2ILI element, the output of the ZI-2IPI element is connected to the first input of the third OR element, the second input of which is connected to the output of the fourth element, the first and second inputs of which are connected to The first and second outputs of the module, the third output of which is connected to the second input of the primary AND, and the output of the third element of the 5th element of the UNEQUAL DIFFERENCE and the first STI, is connected to the first input of the first output input of the third element of the UNEMINABLE element of the UNEQUALITY, output of the COVER, output which is connected to the one that is connected to the first input by the fourth input of the NAND element, the second right OR element, the second input to the third element is UNEQUAL TO one connected to the output of the 0 element. The first input is connected to the fourth IS output. cerned connected module, the fifth output of which is connected to the output of the second member in a yield nonuniformly fourth OR gate. Table 1 Inputs nast-. Information taken from an informaroik .irZII I l 0001Х1Х2 X1VX2 01X1X2 xTvX2 xl X2 V, Y5 XJ. X2 UA V XI X2 U3; VX1X2 V XI X2 Y6 Y5; 10X1X2 xTvxi X2.X2Y7 XI X2 U4 V XI X2 U3VXlX2; 1 1 XI XI} UVX2 Y X2 Y7 where XI and X2 are the signals supplied to the information inputs of the module 1 and 2, respectively; from and U4 - signals applied to the configuration inputs of the module. 3 and 4 respectively. table 2 The state of the inputs of the Number of elements on the Number of elements on which it detects that non-Information is detected is a type of malfunction of the type of constant constant constant 1 for this set the set of states of the inputs X1X2NII inputs 00 01 10 eleven 00 01 10 5, 7, 11, 12, 13 5, 7, 11, 12, 13 5, 7, 11, 12, 13 5, 7, 11, 12, 13 5, 8. 5, 8 5, 8 10, 13 10, 13 10, 13 Continued table. 2