SU1667241A1 - Multifunctional logic gate - Google Patents

Abstract

The invention relates to computing and microelectronics and can be used to implement logical functions Exclusive OR with the ability to confirm the health in the process of functioning as intended. The purpose of the invention is to increase testability. The multifunctional logic element contains six elements AND 6, 7, 8, 17, 18, 21, four elements of 9–12 inequality, two elements OR 13, 22, three elements NOT 15, 19, 20 and majority element 16 and has the ability to function On certain input sets, or when testing it with these input sets, to reveal constant single faults of any of its elements. This improves testability and shortens the troubleshooting time of the multifunction logic module. 1 dw., 2 tab.

Description

The invention relates to computing and microelectronics and is intended to implement logical functions with the ability to confirm the health in the process of functioning as intended.

The purpose of the invention is to increase the testability of the multifunctional logic element.

The drawing shows a block diagram of a multifunctional logic element.

The multifunctional logic element contains five input buses 1-5, of which three buses 1-3 are informational and two buses 4, 5 are control, the first is the third logical elements AND 6-8, and the first is the fourth element UNCONFIGUAL 9 - 12, logical element OR 13, information output 14, first element NOT 15, majority element 16, fourth element AND 17, fifth element AND 18, second element NOT 19, third element NOT 20, sixth element AND 21, additional logical element OR 22 and the control output 23.

In the multifunctional logic element, the first information bus 1 is connected to the first inputs of the fourth 12 and second 10 elements UNEMATICAL, the majority element 16 and the first element AND 6, the second information bus 2 is connected to the second inputs of the first 9 and third 11 elements UNIVERSAL, majority of the element 16 and the first element 6, and the third information bus 3 is connected to the second input of the second element INEQUAL 10,

CX ON VI Yu

the third input of the first element And 6, the first input of the third element UNEMNATABILITY 11 and with the third input of the majority element 16, the first control bus 4 is connected to the first input of the first element NEAR EQUITY 9, the second input of the fourth element UNEQUALITY 12 and the input of the first element NOT 15, The connecting bus 5 is connected to the fourth input of the first Ibis element by the first input of the fifth element And 17, the outputs of the first 9 and second 10 elements of the UNEQUALITY are connected respectively to the first and second inputs of the second element a And 7, the outputs of the third 11 and fourth 12 elements UNEQUALITY are connected respectively with the first and second inputs of the third element And 8, the outputs of the second 7, first 6 and third 8 elements And connected respectively with the first, second and third inputs of the element OR 13, the output of which connected to information output 14, the input of the third element HE 20 and the first input of the sixth element And 21, the output of the first element NOT 15 is connected to the second bypass of the fifth element And 17, the output of which is connected to the third input of the fourth element And 18 and to the second input sh element 1/121, the output of the majority element 1 b is connected to the second input of the fourth element And 18 and the input of the second element NOT 19, the output of which is connected to the third input of the sixth element And 21, the output of the third element NOT 20 is connected to the first input of the fourth element And 18, the outputs of the fourth 18 and sixth 21 elements And connected respectively with the first and second inputs of the additional element OR 22, the output of which is connected to the control output 23.

The proposed module in the absence of faults operates as follows.

In the static state, signals are not supplied to the circuit inputs.

In the dynamics, binary sets of input variables A, B, C, respectively, are supplied to busses 1-3. At the same time, the control signals 4 and 5 are supplied with control signals AND 1, And 2, taking the values of binary constants 0 and 1. In this case, in accordance with the specific values of the control signals And 1 and And 2, the corresponding signal is output from output 14, Functionally output 14 can be described by an expression of the following form:

F Н (А, С) Н (8, И1) УН (В, С) Н (А, И1) ААВСИ2, | de F - function, removed from the output 14;

H (A, B) ABVAB - UNEQUALITY function;

V - logical operation OR. Specific Values of the Controllers

And 1 and 2 signals in the implementation of all functions are given in Table. one.

Example. When the values of the controlled signals are AND 1 O, AND 2 1, element 6 and 6 is opened by signal 2. From the output of the element NORAW KEY 10, the AC VAC function is removed, and from the output of the element NEURAL 11, the function VS v. 15 is removed. In the diagram, the UNEQUALITY 9 and 12 elements select the functions of the controlled inverters in accordance with the operation logic. UNEQUAL DETAILS H (X, I) XI1 / XI, H (X, 1) X and H (X, 0) X. Therefore, from the output of the UNKNOWNABILITY element 9 enters the signal B. From the output of the element And 7, the signal () B is removed, and from the output of the element And 8- (BCVBC) A. From the output 14 of the circuit in this case, the function is removed. (ACVAC) BV (BO / BC) ABVACVBC.

5 Similarly proposed

The scheme implements the remaining functions presented in Table 1.

If a constant logical fault occurs, the output of one of the elements AND 6–8, or UNEQUAL DETAILS 9–12, or OR 13 at the inputs of the elements 18 and 18 and 21, with a corresponding input or test set, the signals

5 1, forming this signal both at the output of any of the indicated elements AND, and through the element OR 22 at the control output 23, signaling the presence of a constant fault in the multifunctional logic element.

For example, in the event of a failure of the type constant 1 at the output of the UNEQUALITY element 9 at the input set 00101 and at the information output

5 14 instead of a logical O signal, a logical 1 signal will be generated, since element 7 from the outputs of the UNEQUAL VALUE 9 and 10 signals will be received by logical 1, which will cause the formation of signals of logical 1 at the outputs of the elements 7 and OR 13.

The presence of a fault will be detected by the control circuit by generating a logical 1 signal at test height 23,

Indeed, in this case, the signals of logical 1 arrive at all three inputs of the element And 21, since on the first input it receives a signal taken from the information output 14, on its second input - from

And 17, which generates a logical 1 signal at the states of control buses, to its third output - from an element NOT 19. that also generates a logical 1 signal, since the output of the major element 16 will be a signal of logical O. element 21 forms a signal of logical 1, which is fed to the input of the element OR 22, which leads to the appearance of a signal of logical 1 at the control output 23, signaling the presence of a malfunction in the multifunctional logic element.

After analyzing the functioning of the multifunctional logic element, test kits are identified that reveal any single constant failure of the elements AND 6–8, UNEQUALITY 9–12 and OR 13. The results of the analysis are shown in Table. 2

Thus, this multifunctional logical element implements the majority functions and functions EXCLUDING OR with self-control, which allows to significantly simplify the diagnostics of both the element itself and discrete devices built with its use.

To check the health and diagnose the proposed item, you can additionally use the test kits listed in Table. 2, which can be used to detect the failed element of a multifunctional logic element, which does not allow for the usual duplication.

Claims (1)

A multifunctional logic element containing three AND elements, four UNEMNATABILITY elements and an OR element, the first information bus is connected to the nerves by the inputs of the first AND element, the second / fourth elements UNEQUALITY, the second information bus is connected to the second inputs of the first AND element, the first, second , of the third and fourth elements NEGATIOUSNESS, the third information bus is connected to the third input of the first element AND, the second input of the second element INQUIRELESS and the first the third element UNEQUAL DETAILS, the first control bus is connected to the first input of the first element UNEQUAL DETAILS and the second input of the fourth element UNEQUALITY, the second control bus is connected to the fourth input of the first element I, the outputs of the first and second elements The second element And, the outputs of the third and fourth elements UNEQUALITY are connected respectively with the first and second inputs of the third element And, the outputs of the second, first and third The other elements of AND are connected respectively to the first, second and third inputs of the OR element, the output of which is connected to the information output of the multifunctional logic element, characterized in that, in order to increase the testability of the multifunctional logic element, the HE element, three AND element and additional element OR, first, second and third information buses are connected respectively to the first, second and third inputs of the majority element, output which is connected to the second input of the fourth element And through the second element NOT to the third input of the sixth element And, the first control bus through the first element is NOT connected to the second input of the sixth element And, the information output of the multifunctional logic element is connected to the first input of the sixth element And through the third element NOT to the first input of the fourth element I. The outputs of the fourth and sixth elements I are connected respectively to the first and second inputs of the additional OR element, the output of which is the contact Aulnay yield. Table 1 table 2 /four