RU2037873C1 - Device for majority signal selection - Google Patents

Abstract

FIELD: automation and computer engineering. SUBSTANCE: device has three n-bit input registers which are connected to inputs of group of n majority selection gates and to corresponding inputs of three groups of n "equality" gates. Outputs of each of these groups are connected to corresponding inputs of AND gates. Outputs of AND gates are connected to inputs of OR gate which output is connected to control input commutator having n channels. Inputs of commutator are connected to corresponding outputs of group of majority selection gates. EFFECT: increased reliability of generation of output signals. 2 tbl, 1 dwg

Description

 The invention relates to automation and computer technology and can be used to work in redundant devices.

 A device is known for majority selection of signals, containing in each channel the first majority element, the information inputs of which are connected to the outputs of the registers, and the output is to actuators, and the information inputs of the device are connected to the information D-inputs of the registers, the control R-inputs of which are connected to the control inputs devices, OR elements, the second majority element, the information inputs of which are connected to the corresponding control R-inputs of the registers, and the output is connected to the first inputs of the two x OR elements, the other inputs of which are connected respectively to the first and third inputs of the second the majority element, and outputs to the control inputs of the first additional element of majority.

 A disadvantage of the known device is the low reliability of the formation of output signals.

 The aim of the invention is to increase the reliability of the formation of output signals.

 The goal is achieved by the fact that in a device for majority selection of signals containing an OR element, the first, second and third n-bit input registers whose outputs are connected to the corresponding inputs of a group of n majority elements, the first, second and third groups of n elements are introduced. , the first, second and third AND elements on n inputs of each and the n-channel switch, while the corresponding outputs of the first, second and third input registers are connected to the corresponding pairs of inputs of the elements oh, second and third groups, the outputs of each of which are connected to the corresponding inputs of the first, second and third elements AND, respectively, the outputs of which are connected to the inputs of the OR element, the output of which is connected to the control input of the n-channel switch, the inputs of which are connected to the corresponding outputs of the group of n majority elements.

 The drawing shows a diagram of a device for majority selection of signals.

 The device consists of the first 1, second 2 and third 3 registers connected to the corresponding inputs of group 4 of n major elements and the corresponding inputs of the first 5, second 6 and third 7 groups of n elements of UNIVERSITY, the outputs of each of which are connected to the corresponding inputs of the first 8 , the second 9 and third 10 AND elements on n inputs, respectively, the outputs of which are connected to the inputs of the OR element 11 connected by the output to the control input of the n-channel switch 12, the inputs of which are connected to the corresponding outputs of the nN 4 majority elements.

 A device for majority selection of signals works as follows.

Let the control word S _k1 with the elements of the code S _1j (j = 1,2.n) go to the input of the first register 1, the control word S _k2 with the elements of the code S _2j to the input of the second register 2, and the control word S _k3 to the input of the third register 3 with code elements S _3j .

The output signal P _j at the output of any majority element from group 4 is formed according to table 1.

Table 1
S _1j 0 1 0 0 1 1 0 1
S _2j 0 0 1 0 1 0 1 1
S _3j 0 0 0 1 0 1 1 1
P _j 0 0 0 0 1 1 1 1
The output signal r _1j (r _2j and r _3j ) of any element. UNIVERSALITY of the first 5 (second 6 or third 7) group is formed according to Table 2.

_Table 2. S _1j 0 0 1 1 S _2j 0 1 0 1 r _1j 1 0 0 1
The output signal r _{1 of the} first element And 8 on n inputs is equal to "1" if S _1j = S _2j . The output signal r _{2 of the} second element And 9 at n inputs is equal to n "1" if S _2j = S _3j . The output signal r _{3 of the} third element And 10 on n inputs is equal to "1" if S _3j = S _1j . The signals r ₁ , r ₂ and r ₃ are equal to zero if the indicated equalities are not satisfied at least for one value of j. r ₁ = 1 if S _1j = S _2j , j = 1,2, n; (1) r ₁ = 0 if S _1j ≠ S _1j , j = m, mE [1,2, n] (2) r ₂ = 1 if S _1j = S _3j ; (3) r ₂ = 0 if S _2j ≠ S _3j , j = m; (4) r ₃ = 1 if S _3j = S _1j ; (5) r ₃ = 0 if S _3j ≠ S _1j j = m. (6)
The output signal K _i (i = 1, 2, 2 ⁿ ) of the switch 12 is formed if the signal R from the output of the OR element 11 is "1". If R = 0, then the output signal is K _i = 0. This is achieved by applying a signal R to the control input of the switch 12.

The signal R = 1, if one of the signals r ₁ , r ₂ or r ₃ is equal to "1" (one of the equalities (1), (3) or (5) is fulfilled, which corresponds to the equality of any two of the three control words S _к1 , S _k2 , S _k3 . If R = 0, equalities (2), (4) and (6) are satisfied simultaneously, then the output signal of the switch is 12 K _i = 0. In other words, K _i = 0, if the control words are S _k1 , S _K2 and S _K3 differ from each other.

The output signal K _{i of the} switch 12 is formed as follows. The signals S _{1j of the} first register 1, S _{2j of the} second register 2, S _{3j of the} third register 3 are fed to the corresponding inputs of the majority elements of group 4. The output signals P _{j of the} majority elements are fed to the inputs of the switch 12, forming a control word P _k , the elements of P _{j of} which are formed in accordance with table. 1 The switch 12 converts the control word P _to the output signals K _i ≠ 0, if the output signal of the element OR 11 R = 1. If R = 0, then K _i = 0. The signal conditioning conditions R are described above.

Assess the reliability of the formation of the output signals To _{i of the} proposed device. The reliability of the formation of the output signals of the switch is crucial in cases where the control words S _k1 , S _k2 and S _k3 are transmitted under the influence of interference. For example, when transmitting control words over a radio link in case of a violation or malfunction in radio communications, the switch may generate a false command K _i , which leads to a violation of the control mode or failure.

.
Вероятность выдачи правильного сигнала предлагаемым устройством
P_п=

.
Вероятность ложного сигнала предлагаемого устройства
P_л= P_к-P_п=

.
Достоверность d формирования выходного сигнала К_i определим в виде
d 1 P_л= 1

+

.
Например, при n=3 d=0,69.We determine the reliability of the formation of the output signals K _{i of the} proposed device under the influence of interference. We believe that the content of the control words S _k1 , S _k2 and S _k3 can be arbitrary and the correct output signal K _i from the output of the switch 12 should be unique. The proposed device generates an output signal K _i in the event that at least two of the three control words S _k1 , S _k2 and S _k3 coincide. Then the probability of issuing an arbitrary signal K _{i the} proposed device
P _to =

.
The probability of issuing the correct signal by the proposed device
P _p =

.
The probability of a false signal of the proposed device
P _l = P _to -P _p =

.
The reliability d of the formation of the output signal K _i define in the form
d 1 P _l = 1

+

.
For example, with n = 3 d = 0.69.

Claims (1)

 DEVICE FOR MAJORITY SIGNALING, containing an OR element, first, second and third n-bit input registers, the outputs of which are connected to the corresponding inputs of a group of n majority elements, characterized in that the first, second and third groups of n elements are additionally introduced into it INDIVIDUALITY each, first, second and third AND elements on n inputs each and n-channel switch, while the corresponding outputs of the first, second and third input registers are connected to the corresponding pairs of inputs of the elements RAV ASSIGNMENT of the first, second and third groups, the outputs of each of which are connected to the corresponding inputs of the first, second and third elements AND, respectively, the outputs of which are connected to the inputs of the OR element, the output of which is connected to the control input of the n-channel switch, the inputs of which are connected to the corresponding outputs groups of n majority elements.

Images