SU1302323A1 - Device for checking read-only memory blocks - Google Patents

Abstract

The invention relates to computing and can be used in test equipment for testing fixed memory blocks, as well as in automation and computing devices. telnoy technology for their nrofi. 1actical) control The purpose of the invention is to test accuracy. USTRMSK TVO S (1, signal generator 1, counters 2 1. elements AND 5, formatized. About address signals, trigger 7, electric circuit OR ill-8, delay element 9, 1H) elements 1 1, switches 12 and 16, the signature analyzer 13. In operation, the device, along with the formation of the signature, alternately dh of each chip of the block 34, a different memory forms the signatures d. 1A of each output of the block 34, the damage or failure of which is determined by section; provides loka. Failure of the output, i.e., the accuracy and control depth increase. 1 il. (Oh (l oo o th o o yu with

Description

The invention relates to computing and can be used in test equipment for testing fixed memory blocks, as well as in automation and computer devices for their preventive control.

The purpose of the invention is to increase the accuracy of the control.

The drawing shows a functional diagram of the device.

The device contains a signal generator 1, the first 2, second 3 and third 4 counters, elements AND 5, drivers 6 address signals, trigger 7, element OR NOT 8, delay element 9, key 10, threshold elements 11, first switch 12, signature analyzer 13, zero potential bus 14, as well as switch 15, second switch 16, containing in turn the first 17, second 18, third 19, fourth 20 and fifth 21 elements and having inputs 22-28 and outputs 29-33. A controlled memory block 34 is connected to the inputs and outputs of the device.

The device works as follows.

When applied to the input 22 of the switch 16, the zero-level potential switch 15 sends the generator 1 signals to the input of the counter 2, the counter 2 overflow signals to the input of the counter 3, the signals from the inverted trigger output 7 to the input of the counter 4, and overflow signals of counter 3, to the input of the element OR NOT 8 are overflow signals of counter 4, and the device operates in the measurement mode of the total signature for each microcircuit of memory block 34. In the initial state, counters 2-4, trigger 7 and analyzer 13 are reset (reset and start circuits are not shown). When the device starts up, generator 1 starts to generate pulses that gamble And 5 elements and change the state of counter 2. At the same time, the address of the scanned block 34 of the permanent memory receives the code of the same address until the counter 2 and the switch 12, all outputs of the fixed memory unit 34 are not interleaved. After that, the state of the counter 3 is changed (by an overflow signal from the output of the counter 2) and the outputs of block 34 are again fired. The generator 1 pulses until the outputs of the block 34 under all possible conditions of the counter 3, orpoonieHbi, and then trigger 17, which through the element OR NOT 8 locks the generator 1.

Since counter 3 generates codes for the lower bits of the address of block 34, which usually select words from a single chip defined by the code of the higher bits of the address, a binary sequence is formed at the output of switch 12, each bit of which corresponds to the contents of one cell of the first chip 34. The analyzer 13 performs the conversion of a binary sequence into a combination of characters — the signature. After the operability or malfunction of the first chip of the checked storage unit 34 is determined, the key 10 is pressed for intermediate

start up device. In this case, the analyzer 13 and the trigger 7 are reset, and the content of the counter 4 is increased by one. Therefore, in the memory block 34 being checked, a second chip is selected, which is controlled in the same way. The control of the memory block 34 in the measurement mode of the total signature is completed after the counter 4 is filled, i.e. all the chips of the memory block 34 are alternately selected and for each of them formed its own signature.

When applied to the input 23 of the switch 16 via the zero potential level switch 15, to the input of the counter 2 is fed. signals from the inverse output of the trigger 7, to the input of the counter 3 - the signals of the generator 1,

to the input of the counter 4 — overflow signals of the counter 3; to the setup input of the trigger 7 — overflow signals of the counter 4; to the input of the OR-NOT 8 element — overflow signals of the counter 2 (the measurement mode of the bit signature), in the initial

 state counters 2-4, trigger 7 and analyzer 13 sbrop1eny. When starting the device, generator 1 starts to generate pulses that gate elements of AND 5 and change the state of counters 3 and 4 until the overflow signal of counter 4 sets trigger 7, which through the element OR - NO 8 locks generator 1. At the same time at the output of switch 12, a binary sequence is formed, each bit of which corresponds to the first bit of all

0 words of the block 34. The analyzer 13 converts the binary sequence into a combination of characters — a signature that the operator compares with the reference sequence and thus determines the health or failure of the output of the memory block 34. Then, a key 10 is pressed for intermediate start-up of the device.

 The analyzer 13 and the trigger 7 are reset, and the contents of the counter 2 are incremented by one. The switch 12 connects to the input of the analyzer 13 second

bit memory 34, which is controlled in a similar way. The control of the memory block 34 in the measurement mode of the bit signature ends after the counter 2 is filled, i.e. all the outputs (bits) of the memory block 34 are selected in memory, and a signature has been generated for each of them. Reference signature for each chip and for

five

Each output of a serviceable block 34 of the permanent memory can be determined experimentally or by mathematical calculations on a computer. It can be recorded and used for visual comparison with a real signature or stored in a computer storage device for automatic comparison of control results.

Claims (1)

Invention Formula Device for monitoring fixed memory blocks, comprising a signal generator, first, second and third counters, AND elements, address signal drivers, trigger, OR-NOT element, delay element, threshold elements, first switch and signature analyzer, with the output of the signal generator connected to the first inputs of the elements AND and the input of the delay element and is the control output of the device, the second inputs of one of the elements AND are connected to the corresponding outputs of the bits of the second counter, the second inputs of the other elements And connected to the corresponding outputs of the third counter bits, elements and outputs connected to inputs of corresponding forms An address signal collector whose outputs are the address outputs of a device whose information inputs are threshold inputs whose outputs are connected to the information inputs of the first switch, the control inputs of which are connected to the bits of the first counter, the output of the switch is connected to the information input of the signature analyzer whose sync input is connected to the output of the delay element, the reset inputs of the signature analyzer and the trigger are combined and are the reset input of devices The direct trigger output is connected to the first input of an OR-IE element, the output of which is connected to the signal generator input, characterized in that, in order to increase the control accuracy, a switch is inserted into it, the control inputs of which are control inputs of the device, information the switch inputs are connected respectively to the output of the signal generator, to the overflow outputs of the first, second and third counters and the inverse output of the trigger; the switch outputs are connected to the inputs of the first, second and third counters, input for setting the flip-flop and a second input of OR-NO element.