SU1288868A1 - Device for phase control of one-phase bridge current inverter with compensating member - Google Patents

Abstract

The invention relates to electrical engineering and is intended to control a single-phase bridge current inverter with a compensating link in the form of a throttle connected via anti-parallel connected thyristors. Introduction of the synchronization of recording the processed feedback signal 31 into the second pulse counter 11, as well as the pulses of the one-oscillator 24, determining the range of the phase shift of the pulses of the driver 29 that triggers the compensating level thyristors, increases the reliability of the current inverter to varying loads. 3 il. SO y 00 00 00 05 bo

Description

one

The invention relates to electrical engineering and is intended to control and regulate a single-phase bridge current inverter with a compensating link in the form of throttle, connected through anti-parallel connected thyristors.

The purpose of the invention is to increase the reliability of the inverter operation for varying loads.

Figure 1 shows a diagram of a current inverter with a compensating link in the form of a throttle, connected through anti-parallel connected thyristors; figure 2 - diagram of the device; FIG. 3 shows voltage diagrams for its operation.

The current inverter (figure 1) contains the thyristors 1 - Ap included in the MO, W

Your circuit, the diagonal of which includes a compensating. link in the form of drossel 5, connected through anti-parallel connected thyristors 6 and 7 and load 8. One of the racks of the inverter contains thyristors 1 and 3, another - thyristors 2 and 4.) The device (FIG .2) contains a master oscillator 9, counters 10-12 pulses, And elements 13-17, a block 18, an analog-to-digital converter 19, first 20 and second 21 reversing pulse counters, a block. 22 comparisons, the first 23 and second 24 one-shot, the formers 25 to 28 of the starting pulses of the thyristors 1-4 of the current inverter and the driver of the starting pulses of the thyristors 6 and 7 of the compensating link. The second inputs of the elements 13 and 14 receive a signal 30 from the output of the overload sensor (when the inverter overloads it becomes equal to zero). The input of the block 18 and the information input of the analog-digital converter 19 receive a feedback signal 31 proportional to the average output voltage. the signal of the inverter, the signal 33 is input to the start of the analog-to-digital converter 19. The reference inputs 32, the corresponding code 32, are fed to the second inputs of the comparison unit 22 and the information inputs of the second reversible pulse counter 21 inalnomu output voltage.

Lockout node 18 is a threshold device, the output voltage level of which is 15.

1288868 .2

It goes from a logical O to a logical 1 upon reaching the input of a given voltage.

On fig.Z depicts pulses 34 at the output of the generator 9, pulses 35 at the intermediate output of the counter 10, pulses 36 - 39 at the output of the formers 25 -28, pulses 40 and 41 at the output of the one-shot 23 and 24, current 42 load; load voltage 43, pulses 44 of driver 29J signals 45 and 46 at the outputs of element 22; current 47 compensating device.

The device works as follows.

The master oscillator 9 generates at the output a high-frequency sequence of pulses 34 arriving at the input of the first counter of 10 pulses, the signal from the direct output of which is fed to the inputs of the formers 25 and 26 of the pulses 36 and 37 of starting the thyristors 1 and 4 of the current inverter, and the signals from the inverse output the output of the formers 27 and 28 of the pulses 38 and 39 of the starting of the thyristors 3 and 2 of the current inverter, with the pulses from the direct and inverse outputs of the pulse counter being fed to the inputs of the formers 26 and 27, respectively, through the first inputs of the 13 and the second 14 elements And, on, the second inputs of which signal overload, ki 30 is equal to a single level with 35 no overload.

20

25

thirty

40

When the current inverter starts, the blocking node 18 generates a zero level at the output, which arrives at the second inputs of the And 15-17 elements, eliminating the possibility of changing the phase shift of the thyristor control pulses 44 and 6 of the compensating link with respect to the pulses 36-39 times the thyristors 1-4 the inverter, and the inverter start-up occurs at a constant phase shift of switching on of the compensating link in a lightweight mode with constant parameters of the active circuit elements. When the output voltage of the inverter reaches a certain value (enters the stabilization zone), the signal level at the output of the blocking node 18

rg is reversed, which makes it possible to alter the phase shift and thereby affect the level of the output voltage of the inverter.

When the current inverter starts, the blocking node 18 generates a zero level at the output, which arrives at the second inputs of the AND 15-17 elements, eliminating the possibility of changing the phase shift of the thyristor control pulses 44 and 6 of the compensating link with respect to the thyristor control pulses 36 to 39 and the inverter starts at a constant phase shift of switching on the compensating link in a lightweight mode with constant parameters of the reactive elements of the circuit. When the output voltage of the inverter reaches a certain value (enters the stabilization zone), the signal level at the output of the blocking node 18

is reversed, due to which it is possible to change the phase shift and thereby affect the output voltage level of the inverter.

The pulses from the output of the master oscillator go to the third inputs of the third 15, fourth 16 and fifth 17 elements, and from the intermediate output of the first counter 10 pulses to the installation input of the counter 11 pulses and to the input of the first single vibrator 23, the output pulses 40 of which determine the forbidden zone of phase shift, is fed to the input of the second one-shot. The output pulses 41 of the second single-vibrator 24., determining the range of change of the phase shift, arrive at the first input of the third element I 15. The feedback signal 31 arrives at the measuring input of the analog-digital converter 19, the start-up pulses 33 of which coincide with the output pulses 35 of the first counter 10 pulses, analog-to-digital converter 19 converts the feedback signal into a digital code,

At the end of the conversion cycle, the pulse 49 from the output of the conversion of the analog-to-digital converter 19 is fed to the control input of the first reversible counter 20 pulses and the data from the information outputs 48 of the analog-digital converter 19 is inserted into the reversible counter 20 pulses. Then the parallel code corresponding to the output voltage of the inverter comes from the information outputs of the first reversible pulse counter 20 to the first inputs of the comparison unit 22, the second inputs of which receive the reference code 32 corresponding to the average value of the nominal output voltage; operation of the analog-digital converter 19. Depending on the ratio of the codes, a single level is formed at one of the two outputs of the comparison unit 22. When a single level is formed at its output of .50, with UBJ, and „o, a single level is formed at its output 51 and with equal codes at both outputs, a zero level is formed that prohibits a change in phase shift, t

In the nominal mode with the arrival of the pulse 35 of the intermediate output of the first pulse counter 10 to the control input of the second pulse counter, the code corresponding to the nominal output voltage is recorded from the information outputs 5 of the second reversible pulse counter 21 to the second counter. A code 32 corresponding to the position of the thyristor control pulses of the compensating link, at which the output current of the inverter 43 is nominal, is entered into the second reversible counter 21 at the time of the start of the inverter. At the moment of the formation of a 4G pulse at the output of the second one-shot 24, the pulses from the first intermediate output of the first counter 10 pulses through the element I and the third counter 12 pulses arrive at the counting input of the second pulse counter.

0 The most significant bit of the second pulse counter generates an overflow pulse, which arrives at the input of the imager for 29 starting pulses of the thyristor 6 and 7 of the compensating link,

5 which provides the necessary gain.

When the output voltage of the nominal voltage is increased, a pulse is generated at the output 51 of the block 22, which allows the pulses from the output of the master oscillator to pass through the AND 16 element to the subtracting input of the first reversing counter 20 and the summing input of the second reversible 5 counter pulses. Thus, the content of the first reversible counter 20 is reduced to a value equal to the reference code 32, and the content of the second reversible counter 21 is increased by the same amount, i.e. it records a code corresponding to the output voltage when equality of the codes arriving at the inputs of the comparator unit 22 is reached, zero levels appear at its outputs and the code changes in the first 20 and second 21 reversible pulse counters cease. The time for converting analogue magnitude to digital and its comparison is determined by the frequency of pulses 35 at the intermediate output of the first counter of 10 pulses and is equal to:

55. 1/2 fewx

where f „is the frequency of the output eg YOU X

the inverter. Since the start pulses of the analog-digital converter 19 coincide with the pulses 35 of the intermediate output of the first counter 10 pulses, KOTopbie records the code information from the outputs of the second reversing counter 31 of pulses into the second counter 11, which corresponds to the previous state of the second reversible counter 21, the inverter output voltage is reduced to a value close to the nominal value due to an increase in the current 47 through the compensating link and the period of the output voltage. The current is increased from - due to the fact that the second AND pulse pulse overflows earlier and the overflow pulse from its output earlier arrives at the shaper 29 of the trigger pulses of the thyristors 6 and 7 of the compensating link. The moment of starting the analog-to-digital converter 19, corresponding to the measurement of the excess at the output of the current inverter, in FIG. 3 corresponds to the time instant €,. Similarly, when the output voltage decreases below the nominal, a single pulse is formed at the output 50 of the comparator unit 22, which allows the pulses from the output of the master oscillator to pass through the element 17 to the summing input of the first subtracting input of the second 21 reversible pulse counters. The content of the first reversible counter 20 is increased to a value equal to the reference code 32 supplied to the second inputs of the comparison unit 22, and the contents of the second reversible counter 21 is reduced by the output voltage value corresponding to the deviation. When equality of the codes to the first and second inputs of the comparison block is reached , at its outputs zero levels appear and the change of codes in the first 20 and second 21 reversible pulse counters stops. Thus, the nominal About the value of the output voltage of the inverter through the period after, for example, at time t began changing its analog-digital converter 19, an overflow pulse arising at the output of the second pulse counter appears later and the pulses 44 of the driver 29 of the starting pulses thyristors 6 and 7 of the compensating link are shifted

to the right relative to the time of zero crossing of the output voltage 43 and the current 47 through the choke 5 decreases, which leads to an increase in the output voltage of the current inverter.

The division factors K, the first counter 10 and K, the intermediate output of the counter 10 pulses are determined by the ratios

TO,

far f

8S

to;

2f

out

five

0

where f

Have

be

- output frequency of the pulses of the master oscillator 9;

- frequency of the output voltage of the inverter Gock,

In the event of an overload or the need for software shutdown of the current inverter, the overload signal 30 at the outputs of the elements 13 and 14 does not receive pulses from the outputs of the first counter 10 pulses

5 to the formers 26 and 27 of the starting thyristors of the 2 and 4 racks of the inverter into the next after the appearance of the overload signal at the outputs of the And 13 and 14 elements of the output half-period

g inverter current.

When the overload is removed, the overload signal 30 becomes equal to 1 and the current inverter resumes operation. The third counter 12 pulses detects a single phase shift step5

ha of pulses 44 at a selected duration of C 2 pulses 41 at the output of the second 24 one-shot, equal to

40

 G T 2 2 Oe

where T „- the period of the pulses at the output

J

one counter of 12 pulses;

n is the size of the second counter 11 pulses, equal to the size of the analog-digital converter 19, the first 20 and second 21 reversing pulse counters.

The frequency of the pulses of the master oscillator is selected from the ratio 55 n, 2 ",

 5G

at o, 0, fc,

 2 4 where s is the maximum time for converting an analog signal to a digital code on the outputs of analog-to-digital converter 19;

the maximum time of refining the digital signal by the comparison circuit 22, the first and second reversible counters, until the codes on the inputs of the comparison circuit are equal.

Thus, the introduction of the synchronization of the recording of the processed feedback signal 31 into the second pulse counter 11, as well as the pulses 41, determining the range of the phase shift of the trigger 44 pulses of the thyristors 6 and 7 of the compensating link, increases the reliability of the current inverter for varying loads.

Claims (1)

Invention Formula I A device for phase control of a single-phase bridge current inverter with a compensating link, containing a master oscillator, the output of which is connected to the input of the first pulse counter, the direct and inverse outputs of which are connected to the thyristor start pulse generator of one of the racks of the inverter and through the first inputs of the first and second elements And - to the shaper of starting pulses of another rack of the inverter, the second inputs of the first and second elements And are intended for connection to the inverter overload sensor, the second account pulse pulses, the output of which is connected to the pulse former behind the thyristors of the compensating link, the third pulse counter and two series-connected one-oscillator, as well as the single shift knot, consisting of the blocking node, the third, fourth and fifth elements, and the first and second reverse pulse counters, a block is compared and an analog-to-digital converter, the information outputs of which are connected to the information inputs of the first reverse pulse counter, the control input of which By connecting the output of the conversion is complete analog-to-digital converter, and its information. O. The outputs are connected to the first inputs of the comparator unit, the second inputs of which are intended to supply a reference code, and the first and second outputs are connected through the first inputs. 5 of the third and fourth elements AND respectively to the summing input of the first reversible pulse counter connected to the subtractive input of the second reversible pulse counter and the subtracting input the first reversible pulse counter connected to the summing input of the second reversible pulse counter, and information outputs 5 of the second reversible pulse counter is connected to the information inputs of the second pulse counter, the input of the feedback signal of the device is connected to the information input of the analog-digital converter and to the input of the blocking node whose output is connected to the second inputs of the third, fourth and fifth elements And, third inputs of which  Connected to the output of the master oscillator, characterized in that, in order to increase the reliability of the inverter for varying loads, the first pulse counter is made with an intermediate output that is connected to the start input of the analog-to-digital converter, to the input of the second counter them 5 pulses, the counting input of which is connected to the output of the third pulse counter, and the output of the second single vibrator is connected to the first input of the fifth element I, the output of which 0 is connected to the counting input of the third pulse counter. Order 7822/56 Circulation 683 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 figure 1