SU1481887A1 - Analog-to-digital converter - Google Patents

Abstract

The invention relates to measurement technology and can be used in automatic measurement systems, as well as in computer numerical control systems. The purpose of the invention is to improve the accuracy of the conversion. To do this, a converter containing a comparator 5 element I 6, a measuring counter 7, a counter 8, a null detector 16, a saw-tooth generator 21, a voltage source 15, a correction block 18, a clock generator 9, a switch 1, a capacitor 2, a block 3 keys, integrator 4, voltage regulator 17, hysteresis comparator 14, decoder 13, digital-to-analog converter 20, voltage source 11, address counter 12, reversible counter 19, comparator 10. 2 Cp f-ly, 6 ill.

Description

3

oo

00 00

figure 1

one

The invention relates to measurement technology and can be used in automatic measurement systems, as well as in computer numerical control systems.

The purpose of the invention is to improve the accuracy of the conversion.

FIG. 1 shows a functional diagram of the converter j in FIG. 2; a basic diagram of a sawtooth voltage generator; in fig. 3 is a schematic diagram of a hysteresis comparator; in fig. 4 is a schematic diagram of a voltage regulator; in fig. 5 is a schematic diagram of the correction block in FIG. 6 - time diagrams of the converter operation.

The converter (Fig. 1) contains a switch 1, a capacitor 2, a block of 3 keys, an integrator 4, a comparator 5, an element 6, a measuring counter 7, a counter 8, a generator 9 of clock pulses, a comparator 10, a voltage source P, an address counter 12 decoder 13, hysteresis comparator 14, voltage source 15, null detector 16, voltage stabilizer 17, correction unit 18, reversible, counter 19 digital-to-analog converter 20, sawtooth voltage generator 21.

The sawtooth generator (Fig. 2) contains operational amplifiers 22 and 23, a capacitor 24, resistors 25-28.

Hysteresis comparator (Fig. 3 contains an operational amplifier 29, resistors 30-33, Zener diode 34 D-flip-flop 35.

The voltage regulator (Fig. 4) contains a two-way stabilizer 36, resistors 37 and 38.

The correction block (Fig. 5) contains a D-flip-flop 39 | elements inne 40 and 41 inverter 42.

The time diagrams (Fig. 6) denote: UA (t) is the graph of the linearly varying reference (reference) voltage UL of a triangular shape and constant slope, which is formed at the direct output of the generator 21; tUftm positive and negative amp / unit voltage values UA; Uy - unknown measured voltage, taken from the output of integrator 4, U e - reference

14818872

the voltage generated by the source 11 Tz is the duration of the measurement cycle, which is equal to the duration of the voltage period, t0 is the beginning of the measurement cycle, which corresponds to the moment of formation of the falling edge

reclosing pulse a.

WITH

T,

0

of this moment, time i) r and time Tee-, ah are the logical reclosing signal, which is formed at the output of the comparator 10. In this case, the trailing edge of the pulse al is formed at time t0 in the rising part of the plot UA (t) when UL is ITE and a is a logical signal for changing the sign of voltage 11L, which is formed at the output of the null detector 1 6. When going over voltage

0 id through signal zero changes its value; and the logical signal of the availability of information in the counter 7, which is formed at the output of the comparator 5. The signal ax changes its value at the moment t of the equality of the voltages Ux and U A. From this point on, the information in the counter 7 does not change 1, t x is the moment of equality of the voltages Ux and 11D, which is identified by the back

0 signal front ah. At this moment

T - x

The time T is calculated. The temporary equivalent of the unknown voltage Ux: Tx

t v

Uon

alternating amplitude-stabilized reference voltage formed at reference output of comparator 1 4. Voltage sign U0n varies synchronously with the sign of the derivative dUA / dtj b0fl-logical signal that changes synchronously with voltage U p. The signal "b" is formed at the inoch. - "... op formational output of the comparator 14-, t ,, is the beginning of the measurement cycle (the beginning of the sweep of the line voltage that starts with the value) t msm the middle of the measurement cycle. This moment the voltage U L takes its maximum value + U

B,., - logical signal

The gating (operation resolution) of the decoder 1 3 and comparator 5. The signal b is generated at the gate output of the comparator $ 14 s - the logical signal of the reference time reference T}, which is formed at the first output of the counter 8j t, is the instant of the reference time reference Te, which is identified front edge of c9 signal. In that

the moment in block 18 checks whether the voltage is equal to zero

te reference time

Te

cc is the logical reset signal of the integrator 4, which is generated at the third output of the counter 8}; the gK-logical turn-on signal of the block 3, which is formed at the fourth output of the counter 8. The signal c is distributed

torus duration 2} d

fk tact discharge condensation impulses, post

drinkers for the time tv to the input

BUT

the counter 7, are formed at the output of the element AND 6j TJa- the duration of the charging current of the capacitor 2, is equal to the duration of the high level of the signal bCTj T paj- the duration of the discharge cycle of the capacitor 2 is equal to the duration of the high level of the signal c,

The converter works as follows.

Measured n input, voltages U1, U2, ..., Un enter the multichannel ADC (Fig. 1) via two-wire communication lines to the information inputs of switch 1, which has n pairs of information inputs and one pair of outputs.

The switch 1 and the decoder 13 together form an analog multiplexer circuit that provides the choice of only one of the n input channels, while blocking the switching of all other (n-1) channels. The selection of the required key group of the switch 1 is performed by the decoder 13 according to the N4 code of the 1st channel address, which cyclically, with a constant period equal to T., is generated in the counter 12 and is fed to the information inputs of the decoder 13.

The time division principle of VDK channels used in building the proposed ADC allows alternately switching n measuring channels during the sampling cycle of each channel equal to T g. Each i-channel is assigned its address N and its corresponding time interval equal to TC, where T C T3 / p.

one

Counter 12 changes ation, and accordingly,

its state - change in t

ITS OUTPUT CODE N u WITH CONSTANT

a frequency equal to the frequency f c I / Tu of the pulse logic signal ac being supplied to the counting input (Fig. 6).

g

five

0

50

five

0

five

The measurement of the 1st input voltage U. begins with its switching at the beginning (il) -ro of the measurement cycle to the inputs of the capacitor 2. The duration of the tact T of the charge of the capacitor 2 is determined by the logical signal bst (Fig. 6), which is fed to Enclosing (enabling) the input of the decoder 2.

The logical signal b blocks or enables the supply of control signals to the control inputs of switch 1. Due to this, the switch 1 can be in two states: in the off state, when all key groups are closed, and in the on state, when the i group of keys is open and the measured voltage is applied to the capacitor 2 plates. high level of the signal corresponds to bc, and off to a low level.

The capacitor 2, carried out the galvanic separation of the input circuits from the output, provides a significant suppression of common mode noise.

To obtain a high speed ADC, you need to select a small capacitance condensate 2. However, direct measurement of the voltage on a small capacitor does not provide a high accuracy of the ADC, since due to the final value of the input resistance of the measuring circuit, the discharge of capacitor 2 will occur during the operation of the analog-to-digital conversion.

Therefore, the capacitor 2 is used in the device as an intermediate storage device (RAM), from which, after the end of the charging cycle, is transmitted through block 3 to the integrator 4,

Unit 3 contains two parallel-connected analog switches that are turned on in the second half of each high level measurement cycle.

him a logical signal with

B to

Signal

SAT) determines the duration of the discharge time of the capacitor 2.

The duration of the discharge cycle significantly exceeds the time constant of the discharge circuit of capacitor 2, which ensures complete suppression of the voltage U; (memorized in the i-th measurement cycle) to the beginning of the next (i + P-th measurement cycle. Therefore, in

the device eliminated the mode of operation of the switches of switch 1 with a double amplitude value of the applied voltage equal to 2U, m. Such a mode is possible in the device without quenching the charge of the capacitor 2, when at the beginning (i + l) ro of the measurement cycle the capacitor 2 stores the amplitude value of the voltage of the U-1st cycle from 1 m

measure, equal and opposite in sign to the amplitude value of the switched voltage U ti + 1) m

To ensure high accuracy of information transfer from the capacitor 2 to the integrator 4, the discharge of the capacitor 2 is performed for a calibrated time through the precision input resistor included in the integrator 4. This ensures the high stability of the transmission ratio of the discharge of the capacitor 2.

The integrator 4 is implemented according to a typical circuit based on an operational amplifier with a capacitor in the negative feedback circuit and using a blanking mode (discharge of its own capacitor), which is performed in the middle of each measurement cycle in the presence of a logical signal with the use of sequential information processing blocks of memory (capacitor 2 and integrator 4) leads to an increase in time spent on servicing each channel.

In order to compensate for these time losses, the device performs parallel processing of information from two adjacent channels during time 1J2. As a result, the duration of the measurement cycle, equal to the time Tc, which in the system with VDK is allocated to service one channel, remains unchanged, although the actual time spent on the channel is ZTc / 2.

Parallel processing of information of adjacent channels is performed in the first half of each measurement cycle, when, together with the switching of the 1st channel, the voltage measurement of the (i-l) -ro channel is measured.

The work of A1SC is based on a known one-time integration method using an intermediate transformation of an unknown voltage U x into a proportional time interval, which is measured

Using clock pulses of an exemplary frequency, the principle of operation of a single integration ADC is as follows.

The unknown voltage Ux is compared with the linearly increasing reference (reference) voltage U l of constant cone. The operation of comparing two voltages, implemented with the help of comparator 5, is performed from the moment 1: "(Fig. 6) the start of the measurement cycle to the instant t x equality of the compared voltages.

From the same moment t0, the pulses of the exemplary frequency f0 begin to accumulate in the counter 7. At the moment t x of equality, the voltage J and the slider Q, the comparator 5 is stopped and the counting of the pulses in the counter ceases. At the same time, the value of the code recorded in the meter 7 is proportional to the unknown voltage.

5 In the ADC, the integrator 4 acts as a source of unknown voltage Uy, which is equal to the measured one. The operation of comparing two voltages is performed on an increasing

0 is a plot of the linear voltage id with the help of a comparator 5, which is controlled by a high level of the logical signal b tT.

At the moment of equality of the compared voltages Ux and UA, the comparator 5 forms the zero level of the logic signal Ux, which is fed to one of the two inputs of element 6, blocking the passage of clock pulses of the reference frequency Ј0, to the counting input of the counter 7, which forms the N 5 proportional code unknown voltage Ux.

The logical signal Ux is

5 sign of the availability of information in the ADC. Its trailing edge, formed by the comparator 5 at time tx, triggers the action of the system, in which the ADC is applied, aimed at reading

- the measurement information from the counter 7 together with the channel address, which is stored in the counter 12.

This operation must be performed by the system until the re-activation pulse is generated d ... co5 "°

The second one performs the initial setup of the ADC.

The linear voltage and, generated by the generator 21, has a symmetrical triangular shape. Longer- its period is taken in the device for the duration T, the measurement cycle, and the time t Mlitl, when the linear voltage U takes its negative amplitude value -UAm, is taken as the beginning of the measurement cycle.

The beginning of the measurement cycle is the time tu, which corresponds to the trailing edge of the reclosing pulse a0, generated at the output of the comparator 10 in the form of a high level logic signal.

The leading edge of the reclosing impulse ae is formed at the moment of equality of the voltage -U e and -U /, on the falling part of the graph), and the trailing edge. - at time t Q, the voltage equals -Ue and -il in the portion of the increase in the linear voltage UA.

The re-activation pulse a0 performs two functions in the converter: first, the function of the initial setting of the ADC at the end of the measurement cycle, during which a reset operation of counters 7 and 8 to zero and an operation of increasing the content of counter 12 by one, and secondly, , the identification function (on the falling edge of the pulse a „) of the moment te.

The accuracy of identifying the start of the measurement cycle depends on the accuracy of the comparator 10 and on the stability of the source 1 1.

From the time t0, the measurement of the unknown voltage Ux begins. Counter 7 counts the clock pulses d 0 of the reference frequency f 0 for the time Tx (t x - tQ) from the time t 0 to the time t x the comparator 5 trips. This time is proportional to the amplitude of the unknown voltage Ux. Its binary equivalent code N "is stored from the moment of the counter 7. The value of Nx is determined by the following expression:

Nx TX / T0 KVX,

T x is the time during which the accumulation of pulses d occurs in the counter 7 $ T0 - the period of following pulses of the model frequency fa; K - coefficient of proportionality.

synchronization work transform each measurement cycle

carried out using the counter 8, which (acting as a divider of the reference frequency f 0, ensures the formation of a sequence of logic signals se, c „and c

FK

The leading edge of the pulse with 3 corresponds to the instant t e of checking the condition of zero linear voltage and “on the growing part of the graph U / v (t). The impulse with e is used to form in the block 18 a corrective action ensuring the constant rate of increase of the linear voltage U l.

The reset pulse c0, generated at the end of the measurement cycle, switches integrator 4 into the quenching mode, and its inversion, pulse c0, initiates the formation of the trailing edge of the gating pulse, b st, which is generated by the comparator 14. The key B of the activation of keys of block 3 is formed after setting

zero of the integrator 4. It connects to the two inputs of the integrator 4 the terminals of the capacitor 2, ensuring its full discharge by the time of the formation of the reclosing impulse av.

Comparator 14 can be in two stable states: in state 1 and in state O. In these states, at its reference output, which is connected to a common point

the connections of the resistors 30 and 31 form, respectively, two equal in magnitude values of the analog voltage U,

: + U PP and -U

op oo u on A change in the state of the comparator 0 occurs at instants t and t ax i.e. at the beginning and in the middle of each measurement cycle. The switching of the comparator 14 at the time tMMH is used to form at its strobe 5 Router the logical signal b st. This signal is generated by the D-flip-flop 35.

D-flip-flop 35 is cocked on the C-input by the leading edge of the bo signal at the time t MM) | and is reset after a calibrated time with signal 0.

In order to increase the stability of the linear voltage fluctuation frequency f u r .UA of a triangular shape, stabilizer 1 7 is used. Stabilizer 1 7 converts the voltage generated at the output of amplifier 29, which depends on the fluctuations of the supply voltage, into a stabilized reference voltage Uon,

Consider the formation of a linear voltage sludge without taking into account the effects of voltage U

Suppose that the comparator 14 is in the state 1 - the moment cmin. Then the voltage + U „„ is formed at its reference output. In this case, an increasing linear voltage is formed at the forward output of the generator 21, and a decreasing one at the inverse voltage. When the value of the linear voltage at the analog input of the comparator 14 exceeds the modulation threshold, i.e. reaches its negative amplitude value -UftTn, it will switch to

O state - moment t

Max

In this case, at the linear output of the comparator 14, a negative voltage value 1010p is formed. Then, from the direct output of the generator 21, a decreasing linear voltage U will be removed, which will decrease until its magnitude reaches the trigger threshold, i.e. when at the reference input of the comparator 14 the input voltage reaches + UAm,

At this moment t М1ДН linear voltage U. will reach its amplitude

The value of Ult5, the comparator 14, will again return to state 1, and the line voltage UA will begin to increase again. A new measurement cycle will begin.

Thus, at the output of the generator 21, a linear voltage UA of a symmetrical triangular shape with a period of oscillation oscillations equal to

T c. 4 R ° CUKg „

(ABOUT

de R op is the input resistance of the generator 45 on the reference input, which is equal to the sum of the resistances of the resistors 25 and 26;

C u is the capacitor capacitance 24 in the Q feedback circuit of the generator 21;

To rk - the transfer coefficient of the comparator 14. It is determined

from equality U

on

kg and

The rate of change of the linear stress U p, which can be estimated by the coefficient of the Copop steepness (characterizes the angle of inclination of the branches

with

Q 5

0

50

§

0

five

the time characteristic UA (t) of the generator 21), is determined by the expression

v du l, U lt-K g G9ch

l op n - t g)

at 1 c, to C and

Where K Of | - the coefficient of the reference slope when controlling the generator 21 on the reference input.

As can be seen from expression (2), the required slope of the branches of the time characteristic UA (t) can be easily achieved by choosing certain values of the parameters R op and C, However, due to the same parametric dependence, the coefficient Cop can change over time due to aging of the elements and as a function of temperature.

To stabilize the slope of the linear voltage 11L, the device provides for the formation of a correction signal (correction current) using the DAC 20, which is obtained from the reference voltage U6k correction taken from the output of the stabilizer 17. The voltage U0k is the reference voltage of the DAC 20. Therefore, the magnitudes of the opi UOK are connected by a linear relationship and their signs are the same.

By changing the correction code Nk, which controls the transfer ratio of the DAC 20, you can change the correction current, which is fed from the DAC 20 to the correction input of the generator 21, accelerating or slowing down the rate of change of the linear voltage of the PL.

The effect of the corrective action of N "Ha on the steepness of the linear voltage U n formed can be estimated using the coefficient and К of the correction of the slope equal to

U OKNK

LC

RkcM 2

where Rb is the resistance of the correction circuit, consists of the sum of the input resistances of the stabilizer 17, the DAC 20 and the input resistance of the generator 21 at the correction input; m is the DAC resolution 20.

Taking into account the correction signal, the required constant slope of the branches of the time characteristic U rt (t) can be estimated using the reference steepness coefficient Ke, which is the sum of the coefficients K op and d

K z K op + and K. const.

The task of correcting the steepness is to maintain a constant Ke at the Cope var by changing the value of / JK.

To ensure symmetry when correcting the linear voltage steepness U L in both directions (upwards and downwards and K), it is advisable to choose the initial correction code N from the middle of the correction code as the operating point of the DAC 20.

those. fulfill condition

„“ “-H No 2

Then the initial setting of the required coefficient K 3, carried out by changing the resistance, Ronr should be made if there is an initial correction code N on the digital inputs of the D / A converter 20

The required reference slope of the branches of the time characteristic U (t) of the generator 21 can be achieved by assigning one of its branches, for example, increasing, to two selected reference points, through which only one straight line, for example, with the required slope, can be drawn. equal to the coefficient ke.

In the device, the lower reference point of the graph U (t), corresponding to the moment t0, is specified by the source 1 1, at the output of which a reference voltage equal to -U is formed.

The upper reference point corresponding to the time t3 is specified by the source 15, for which the zero voltage is used - the voltage of the signal ground,

Thus, the lower reference point of the linear voltage reference graph UA has coordinates (-U5, t0), and the upper reference point contains coordinates (О, t3). In this case, the equality

,

TO

s1

(four)

A corrective action can be formed as follows: fix the moment t0 of the equality of the stresses -U j and -U And on the ascending segment of the graph UA (t); from the moment to

count the reference time T e and fix the time t; at time t, check the condition, moreover, if UA 0 (the rate of change of voltage is greater than normal), then decrease the value of the correction code Nk in the counter 19 by a quantum, and if 11L 0, then increase the value of the code N by kvan Variant 0 is not analyzed, since the conditional check UAO is usually implemented on a comparator that has only two output states:

H and O

Therefore, when the value is U

closeJQ 15

35

0

Mu to zero, which corresponds to the steady state, the system of automatic control of the slope will be in self-oscillating mode with an amplitude of self-oscillations of +1 discrete.

The formation of the correction code N is as follows. At time t 0, counter 8 is started and

25 begins the countdown. At time t3, the counter 8 forms the leading edge of the logical signal c, which is fed to the C input of a D-flip-flop 39. To the D input of this D-flip-flop 39

30, a sign logic signal is output from the output of the null detector 16.

The null detector 16, which is a comparator, can be in two states: in state 1, when U L 0, and in state O, when U L 0.

If, at time t, the sign input of block 18 receives a high level of a sign logic signal, then D-flip-flop 39 goes to state 1. If it is 0, then D-flip-flop 39 is set to state O.

The logic signal Lop, arriving at the moment t max of the counting input of block 18, polls the outputs of the D-flip-flop using elements 40 and 41 and generates a correction pulse Q at one of the two outputs of block 18 (the moment tMul)) changes the count of 19 to a quantum.

The linear voltage slope correction operation is performed in 5 each measurement cycle.

In the steady state, the correction pulses arrive alternately at the summing and subtracting inputs of counter 19.

/

14

Thus, in comparison with the known, the proposed converter has the following advantages: it provides an increase in the accuracy of conversion due to digital correction (with high resolution) of the steepness of the linearly increasing reference voltage over two reference voltages, provides suppression of the common-mode noise by galvanic separation input circuits from the measuring circuit using a capacitor, allows to simplify the technical implementation of the converter by using the principle of ELENI channels improves the controllability by reducing the volume of the individual equipments of each measuring channel.

Claims (2)

1. Analog-to-digital converter containing the first comparator, the output of which is connected to the first input of the element I, the second input of which is connected to the output of the clock generator and combined with the counting input of the pulse counter, and the output element I is connected to the counting input of the measuring counter, the reset input of which is combined with the input of the pulse counter, the first output of the pulse counter is connected to the clock input of the correction unit whose sign input is connected to the zero output of the detector, the first input of which is combined with the first information input of the first comparator and connected with the direct output of the sawtooth generator, the second input of the null detector is connected to the output of the first voltage source, so that, in order to increase the accuracy conversions, a key block, a second comparator, a switch, a cumulative element made on a capacitor, an integrator, an address counter, a voltage stabilizer, a hysteresis comparator, a decoder, a reversible counter, a digital-analog converter, a second voltage source 1, the output of which is connected to the first input of the second comparator, the second input of which is combined with the first input of the zero detector, and the output is connected to the reset input of the pulse counter and to the counting input of the address counter H 0 five 0 five 0 five 0 five the outputs of which are connected to the corresponding inputs of the decoder and are channel address buses, the outputs of the decoder are connected to the corresponding control inputs of the switch, the gate input of the decoder is connected to the gate input of the first comparator and connected to the gate output of the hysteresis comparator, the information output of which is connected to the read input and the analog input is with the inverse output of the sawtooth generator; the reference output of the hysteresis comparator is With the input voltage regulator and the reference input of the sawtooth generator, the reset input of the hysteresis comparator is connected to the second output of the pulse counter, the third and fourth outputs of which are connected respectively to the control inputs of the integrator and the key block, the information inputs of the switch are input buses, the first output of the switch is combined with the first output of the capacitor and connected to the first information input of the key block, the second output of the switch is combined with the second output of the switch and the second information input of the key block, the first and second outputs of which are connected respectively to the first and second inputs of the integrator, the output of which is connected to the second information input of the first comparator, the output Kofoporo is the information availability signal, the outputs of the measuring counter are corresponding output tires, the output of the voltage regulator is connected to the reference input of the digital-to-analog converter, the output of which is connected to the correction input of the sawtooth generator EIW DAC data inputs connected to respective outputs of down counter, adder and subtractor whose input is connected to the first and second outputs of the correction unit. 2. The converter according to claim 1, characterized in that the correction unit is executed on a D-flip-flop, an inverter and the first and second AND-NES elements whose outputs are respectively the first and second outputs 26 28  23 2 32 3 / Jt1 Fig.Z Figi w 7L X //////} / Y /// A