SU1501269A1 - Electric signal coder - Google Patents

Abstract

The invention relates to a pulse technique, can be used in the systems of discrete transmission of audio, telemetry and other signals. And it improves speed and accuracy. A device containing analog-to-digital converter 5, recorders 8, 9, analog storage device 2, clock generator 1 of sawtooth voltage, prohibition element 11, counter 7, measuring differential amplifier 4, prohibition elements 12, 14, delay element 13 and the element OR 10 1 s. f-ly, 9 ill.

Description

Ja.

Ut

(L

- HMtaitt V LYP,

Feb. 1

315

The invention relates to a pulsed technique and can be used in systems for the discrete transmission of audio, telemetry and other electrical signals.

The aim of the invention is to increase speed and accuracy.

FIG. 1 shows a functional device diagram in FIG. 2 is a functional block diagram of the control unit; in fig. 3 - electrical circuit diagram of a sawtooth generator; in fig. 4 is an electrical circuit diagram of an analog storage device; in fig. 5 is an electrical circuit diagram of a measuring differential amplifier; FIG. 6 is a functional diagram of the first matching block; in fig. 7 is a functional diagram of the second coincidence unit in FIG. 8 is a timing diagram of the operation of the device; FIG. 9 shows the dependence of the difference between the voltages of the sawtooth generator and the analog storage device (2) between adjacent pulses.

A device for encoding electrical signals (Fig. - 1) contains an sawtooth voltage generator 1, an analog storage device (AMC) 2, a clock generator 3, a measuring differential amplifier A, an analog-to-digital converter (ADC) 5 of parallel type, a control unit 6, a counter 7, registers 8,9,

the element OR 10, the elements 11, 12 of the prohibition, the element 13 for ;; holders, the element 14 of the prohibition.

The control unit 6 (Fig. 2) contains prohibition elements 15-17, counters 18, -19, coincidence units 20, 21, pulse generator 22, delay element 23.

Sawtooth generator 1 (FIG. 3) contains an OR-NOT 24 element, transistors 25-21 zener diodes 28, operational amplifier 29, transistors 30, resistors 31, transistor 32, capacitors 33, zener diodes 34, 35.

Analog memory device (Fig. 4) contains the element OR NOT 36, key 37, transistor 11 | J8, resistors 39, capacitor 40, zener diodes 41, 42.

94

Measure l 1) The LOW differential amplifier (Fig. 5) consists of operational amplifiers 43-46, resistors (7-49, diode 50.

The match block 20 (FIG. 6) contains the elements NOT 51, the AND-NOT element 52,

Block 21 matches (Fig. 7) contains the elements NOT 53, the element OR 54,

AND-NOT element 55.

The device works as follows.

Analog input signal U st-blunt to the first input of the AMC 2 to the second

Its input signal is supplied from the control unit 6, which opens the key 37 of the AZS 2 for the time required for the signal storage Uj-. The signal that opens the key 37 AZS 2, also served

and a first input of the generator 1 (Fig. 8b), opening its transistor 32, through the internal resistance of which the discharge of the capacitor 33 occurs to the initial value. At the moment of closing the key 37 of the ABC 2 and the key 32 of the generator 1 to the second input 1 of the generator 1, a prohibition element 14 from the control unit 6 is given a signal (Fig. 8c), which opens the current switch transistor 26. The key formed by transistors 25, 26 is made according to the current switch circuit. The state is open; that key corresponds in this case to the situation when the transistor 26

open, and the transistor 25 is closed. The private key of the private key corresponds to the opposite situation. Through the current switch, the capacitor 33 of the generator 1 is charged with direct current.

from the current generator, including the transistor 27, the zener diode 28 and the operational amplifier 29. At the same time, the first input of the counter 7 (Fig. 8h) and the second input of the A / D converter 5 (Fig. 8i) begin

clock pulses from 6 through elements 13,11,12 respectively arrive. The signals from the outputs of the AMC 2 and the generator 1 are fed to the inputs of the measuring differential amplifier

4. The output signal of amplifier 4 is fed to the first input of parallel 5, which is adjusted so that it perceives only positive or only negative differences.

From the output of the measuring differential amplifier 4, which corresponds to the states of the signals at the inputs of the amplifiers 4, at which the signal from the output of the generator 1 in absolute value

exceeds the output signal (Fig. 8e).

The gain of amplifier 4 is chosen so that the maximum difference that may occur on its first step, and then, on the first input of the ADC 5, between the time that the voltages are equal at the inputs of the amplifier 4 and the next after this clock pulse at the second input of the ADC 5, corresponded to the maximum value of the input C) of the selected ADC 5.

We see the need to use NIN inverse codes from the output of the ADC.

The moment of coincidence of the voltages at the inputs of the measuring differential amplifier A may coincide with the clock pulse at the second input of the ADC 5 or occurs at any time between adjacent clock pulses (Figs. 9a, b).

Clock pulses arriving at the counting input of counter 7 must be delayed with respect to clock pulses arriving at the clock input of the ADC 5 for a time that allows the clock pulse that captures the first occurrence of the units at the output of the ADC 5, the counter input, what is the delay element 13 for. The magnitude of this delay depends on the element base used to implement the proposed device. Consider the operation of unit 6 (Fig. 2) in conjunction with the operation of the device. Impulses from the output

Consider the limiting case when the situation of coincidence of the voltages 25 of the clock generator 3 (Fig. 8a) occurs at the inputs of the measuring differentiation to the second inputs of the elements of the 15-amp amplifier occurs simultaneously with the ADC clock pulse (with the moment of fixation of the

ADCs in its output register (Fig. 9a). This means that the lower bits of the output code are zero, i.e. the output code is determined by the number of clock pulses counted by counter 7 until the voltage coincides at the inputs of the measuring differential amplifier 4. However, in this case, the appearance of a code other than zero, at the output of the ADC 5 can occur only with the next clock pulse applied to ADC clock input 5. With the above matching of the gain of the measuring differential amplifier A with the input voltage range of the AOC 5, the voltage at the output of the amplifiers changes by an amount corresponding to This is the maximum value of the input voltage of the ADC 5, which leads to the appearance of units at once in all bits of the ADC code 5. But, as mentioned above, the lower bits of the output code must be zero. Consequently, the codes from the output of the ADC 5 must be taken with inversion. In other words, the ADC code, which characterizes the excess of the signal of the generator 1 over the input signal and between the instant of coincidence of these

35

40

17 ban. Let counters 18 and 19 reset. In this case, the signal from the first output of block 20 of coincidence (Fig. 8b) permits the passage of pulses of the clock generator through element 15 to the first input of counter 18, and the signal from the second signal of block 20 (Fig. 8c), which is inverse with respect to the signal, taken from the first output, prohibits the passage of pulses of a 1k generator to the first input of counter 19 through element 17. The matching code on block 21 is selected depending on the accuracy of the measurement by the positive method. For example, with a six-digit analog-to-digital conversion, eight leading bits of a code can be determined by a counting method, and eight younger bits can be determined using an eight-bit parallel ADC. In this case, the match code on block 2 | corresponds to the number 256 in binary code. AT

With 50 other device building options, this number can be changed. The match code on block 20 is selected from the ratio of time intervals: the interval required for

its memorization of the reference of the signal being converted, and the interval necessary for measuring the signal. With the appearance at the outputs of the counter 18, a matching code on the first output of the block 20

45

-Q 15

12696

voltage of the measuring measuring differential differential amplifier and the first

clock pulse that fixes it

The excess of VLCP 5 corresponds to a value that must be subtracted from the maximum value of the code of the SFC 5, and the result of such a difference is an inverse code.

Clock pulses arriving at the counting input of counter 7 must be delayed with respect to clock pulses arriving at the clock input of the ADC 5 for a time that allows the clock pulse that captures the first occurrence of the units at the output of the ADC 5, the counter input, what is the delay element 13 for. The magnitude of this delay depends on the element base used to implement the proposed device. Consider the operation of unit 6 (Fig. 2) in conjunction with the operation of the device. Impulses from the output

20

25 of the clock generator 3 (Fig. 8a) is fed to the second inputs of the elements of the 15-clock generator 3 (Fig. 8a) is sent to the second inputs of the elements 15-

17 ban. Let counters 18 and 19 reset. In this case, the signal from the first output of block 20 of coincidence (Fig. 8b) permits the passage of pulses of the clock generator through element 15 to the first input of counter 18, and the signal from the second signal of block 20 (Fig. 8c), which is inverse with respect to the signal, taken from the first output, prohibits the passage of pulses of a 1k generator to the first input of counter 19 through element 17. The matching code on block 21 is selected depending on the accuracy of the measurement by the positive method. For example, with a six-digit analog-to-digital conversion, eight leading bits of a code can be determined by a counting method, and eight younger bits can be determined using an eight-bit parallel ADC. In this case, the match code on block 2 | corresponds to the number 256 in binary code. AT

Other options for building the device may change this number. The match code on block 20 is selected from the ratio of time intervals: the interval required for

storing the reference of the signal to be converted, and the interval necessary for measuring the signal. With the appearance at the outputs of the counter 18, a matching code on the first output of the block 20

a signal appears that prohibits further passage of the pulses of the clock generator at the first input of the counter 18. At the same time, a signal appears at the second output of block 20 allowing the pulses of the clock generator to pass through the element

17 at the first counter input 1.9. At the same time, the pulses from the output of the displacer 17 of block 6 arrive at element 1 and through element 13, at element 11. From the output of element 11, the pulses go to the first input of counter 7 (Fig. 8i), and from the output of element 12 to the second input LTSP 5 (Fig. 8h). At the first inputs of elements 11 12, a prohibition signal is received (Fig. 8g). When at least one unit appears (if we argue with respect to the inverse code, then at least one zero), a prohibitance signal is generated in the output ADC code (Fig. 8g). This signal stops the clock pulse to the ADC 5 and the counter 7. At the same time, the same signal through the element 14 stops the charge of the capacitor 33 of the generator 1, which prevents the ADC 5 from being overloaded on the input. When the code 19 on the outputs of the counter appears at the output of block 2, a signal appears allowing the pulse generator to pass through element 16 to the second inputs of counters 18, 19. With this pulse, counters 18, 19 are reset to zero (Fig. 8e) . Then the operation cycle of the control unit is repeated, etc. The outputs of the blocks 20, 21 generate signals intended to control the operation of the AAM 2 and the generator 1. The output code is obtained as follows. The higher bits of the code are the number of Impulses counted by counter 7 until the voltage from the generator 1 of the sawtooth voltage coincides with the signal from the output of the АЗУ 2, and the lower bits - the inverse code from the output of the ADC 5, corresponding to the value of the voltage overshoot the output of the sawtooth generator over the signal from the output of the ASC 2 for the interval between the instant of coincidence of the voltage values and the instant of the next clock pulse. Polling pulses arriving at registers 8, 9 are formed by shaper 22 (Fig. 8d). The beginning of these impulses

Dolly C1; 1 and 1 set at the beginning of the time intervals intended for storing the reference signal.

The impulses arriving at the second input of the counter 7, which are intended to set the counter to the zero state (Fig. 8e), are delayed with respect to the pulses arriving at polling registers 8.9 (Fig. Br) in element 23 of block 6. Delay value must meet the polling pulse duration of registers 8,9.

Amplifier 4 (Fig. 5) works as follows.

, Amplifiers 43, 44 operate in voltage follower mode. High input resistances of the amplifiers 43,

44 and in one case, the discharge of the capacitor 40 in the AAM 2 during the time period of storing the signal is prevented; in the other case, the linearity of the output voltage of the generator 1, sawtooth voltage is deteriorated. Operational amplifier 45 serves to increase the difference between the voltages supplied by the AMC 2 and generator 1. The gain of the operational amplifier 45 depends on the maximum value of the input voltage. The magnitude of the coarse gradation (the magnitude of the gradation in the analog-digital conversion by the pulse counting method) will be

JU

Ubx

tn

P log.m

where Ug is the maximum value

input signal L m - the number of code bits at

analog-to-digital conversion by the pulse-counting method.

The gain of operational usshshtel 45 will be

™ U§ "-Y 4.2,

ai

gr

where and. The ADC has the maximum voltage at the input of the parallel ACC.

The specified gain of the operational amplifier 45 is defined by resistors 47.48, Resistor 49-1 is chosen as large as the resistor 48, and serves to obtain identical input circuits of operational amplifier 45. Operational amplifier 46 operates in repeater mode. voltage and serves to obtain a low output resistance of the measuring differential amplifier, which ensures the work on the input capacitance of the parallel ADC 5. The diode 50 serves to limit the positive differences arising from the output operational amplifier 45, which prevents overloading at the input of the parallel ADC 5. The drift zero stabilization of the differential amplifier must be maintained within half of the lowest gradation of the resulting analog-digital conversion.

Claims (2)

Invention Formula D. A device for encoding electrical signals, comprising an analog-to-digital converter, first and second registers, an analog storage device, the first input of which is an input bus, serially connected clock generator and a control unit, the first output of which is connected to the first input of the sawtooth voltage generator and the second input of the analog storage device, the first prohibition element and the counter connected in series, the second and third outputs of the control unit are connected respectively To the second input of the counter and to the first inputs of the first and second registers, and the second inputs of the first and second registers are connected respectively to the outputs of the counter and analog-to-digital converter, the outputs of the first and second registers are respectively the first and second output buses, characterized in that in order to increase speed and accuracy, the measuring differential amplifier is introduced into it the second and the third prohibition element, the delay element and the OR element, whose inputs are connected to the corresponding output am analog-to-digital converter, and the output - to the first inputs of the first, second and third elements of the prohibition, the second input of the first ten 15 269 O the prohibition element is connected to the output of the delay element, the input of which is combined with the second input of the second prohibition element and connected to the fourth output of the control unit, the fifth output of which is connected to the second input of the third prohibition element whose output is connected to the second input of the sawtooth voltage generator, the output of which connected to the first input of the measuring differential amplifier, the second input of which is connected to the output of the analog storage device, and the output to the first input of the analog-digital converter azovatel, the second input of which is connected to the output of the second member prohibition. five 0 five 0 five 0 2. The device according to claim 1, wherein the control unit is executed on three prohibition elements, two counters, a pulse shaper, a delay element, two coincidence units, the first output of the first connection unit is connected to the first input of the first prohibition element and is the fifth output of the block, the second poi i output of the first block of coincidence is connected to the input of the pulse shaper, the first input of the second prohibition element and is the first output of the block, the inputs of the first and second coincidence blocks are connected respectively to the outputs of the first first and second counters, the first input of the first counter is connected to the output of the first prohibition element, the first input of the second counter is connected to the output of the second prohibition element, which is the fourth output of the block, the second inputs of the first and second counters are combined and connected to the output of the third prohibition element, the first the input of the third prohibition element is connected to the output of the second coincidence unit, the second inputs of the first, second and third prohibition elements are combined and are the input of the block, the output of the pulse shaper is connected to in House delay element and is the third output of the delay element output is the second output unit. R Entrance, ir L., Tl I FIG. 2 Fig.Z R f 39 1 39 39 39 J FIG. FIG. five fayeb Uruannn n p p p П П П П П П P. / gp, and fie.Z