SU1359872A1 - Device for controlling d.c.voltage-to-three-phase quasi-sinusoidal voltage converter - Google Patents

Abstract

The invention relates to converter technology and can be used in the construction of sources of secondary power supply of both centralized and decentralized TimoB in all cases when improved weight and dimensions and improved quality of converted electricity are required. The aim of the invention is to improve the quality of the converted electricity by increasing the content of the main harmonic and reducing the harmonic ratio of the voltage and current. The converter provides a constant voltage converter into a three-phase, quasi-sinusoidal, as well as regulation of its value. The converter includes a modulator in the form of four key racks, three single-phase. a transformer, three demodulators on ac keys, and a control device equipped with a trigger and an element 2I-NOT. The construction of logical nodes provides the formation of a predetermined voltage and its regulation. 6 Il. (L o :) ate with 00 | ND

Description

ten

sixteen

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11359872

The invention relates to converter technology and can be used in the construction of sources of secondary power supply of both centralized and decentralized types in all those cases when improved weight and dimensions and improved quality of converted electricity are required.

The aim of the invention is to improve the quality of the converted electricity by increasing the content of the main wind and reducing the voltage and current harmonics.

Fig. 1 is a circuit diagram of a converter; Fig. 2 shows the proposed device for controlling the converter; Fig. 3 shows timing diagrams illustrating the principle of generating control signals by converter keys; 4 shows timing diagrams for explaining the principle of forming the output phase voltage on a load with one adjustment angle; FIG. 5 shows timing diagrams of two-phase voltages on the load and linear voltage between these two phases at o (on Fig. 6 shows the dependences of the harmonic coefficient of the load current of the converter for the prototype — a and for the proposed grid — b,

The converter (fig. 1) contains a modulator 1, which is complete in the form of four racks of switches 2-9 (in fig 1, for example, in the form of a transistor shunted by a reverse current diode) with control inputs Ml, Ml - M4, M4. One ends of the primary windings 10–12 of three single-phase transformers 13–15 are connected to the middle points of the racks of keys 2–7, the second ends of which are combined and connected to the middle point of keys 8–9 of the fourth rack. The secondary windings 16–18 are connected to three single-phase demodulators 19–21, Demodulators can be made using any single-phase scheme (for example, single-phase bridge) on fully controlled AC switches. In FIG. 1, demodulators 19-21 are made according to a scheme with zero accurate keys 22-27 with controllers.

thirty

35

40

45

50

whoa

inputs DM1, DMG - DMZ, DMZ, Recycled. in the windings 16-18 in this case are made with a midpoint which

at that 19 30

le c k de d on s me t a t a c h i h k to a n c v c on M4 M4

us dy no but in measure of the distance 1

6

0

five

0

five

0

is one of the outputs of demodulators 19-21 combined into a common point. Other outputs of demodulators 19-21 form output terminals 28-30 (A, VUS) of the converter.

The converter control unit 31 shown in Fig. 2 includes a frequency adjuster 32 connected to the first 33 and third 34 frequency dividers, the outputs of which are connected to the inputs of the logic element 2I-HE 35. The output of the latter is connected through the second frequency divider 36 with the first control input of the gas-channel distributor of 37 pulses. The output of the first frequency divider 33 is also connected to the counting input of the first 1K-flip-flop 38, and the output of the third frequency divider 34 to the counting input of the second flip-flop 39 Direct and inverse outputs Q, Q of the first 1K-flip-flop 38 - development node (not shown) with control inputs M4, M4 of keys 8, 9 of modulator 1 so that M4 Q,. To the setup input I of the first trigger 38, the output of element 2I-NO 35 is connected, and to the setup input I of the second 1K trigger 39 - the output of the second frequency divider 36. The six-channel distributor 37 of pulses is made according to a scaling circuit with cross-links, for example, on three main 1K-triggers 40-42, counting inputs KOTQpbix. connected to the first input / output of the second frequency divider 36. Para-phase outputs Q, Q, - Qj, J5 of the main IK-flip-flops 40-42 are connected to

five

0

The installation inputs of the three additional 1K-flip-flops 43-45, the counting inputs of which are combined, form the second auxiliary input of the six-channel distributor 37 pulses and are connected to the output of the logic element 2И-НЕ 35. Three logical nodes are also included in the control block 31: node 46 generating control signals — keys 2–7 of modulator 1, control signal generating unit 47 using keys 22–27 of demodulators 19–21 and auxiliary logic node 48, in addition to these nodes, to ensure control of the output voltage wives A modulator 49 of the width of a pulse is introduced, which is synchronized from the first 33 (the dashed link

313598724

in FIG. 2) or the third 34 divider type D OR 68 — MH + + frequencies or may be autonomous. + element outputs

Auxiliary logical node NOT 70 - signal M2, -71 - MH. Outputs 48 contains two channels. The first node of the node 46 is connected through an amplifier to include a series-connected element ZI-NE 50 and a 2-ZI-2IL 51 element. The connection between the outputs of the first 38 and second 39 IR triggers, the output S of the modulator 49 of width pulses and inputs of elements 50, 51 are performed implementing the following logical functions: ira output element ZI-NOT 50,. and the output element 51 F Q, Q S Q, Output F

Develop a node with control inputs Ml, Ml - MH, MH of keys 2-7 of modulator 1.

Node 47 is also three-pronged. Each channel consists of a 2-2I-OR 72-74 element in series and a NOT 75- 77 element. Connected to the distributor 37 pulses, nepBbw 1K-trigger 38 and

15 auxiliary logic node 4B

provide the implementation of the following logical functions; at the output of the element 2-2И-OR 72 - DM QQ | -lO, Q, Qf + IQf, 74 - the logical node 48 contains by -20 QiQf IQ4 outputs of the H elements, therefore the switched on element NE 75 forms the signal DM1, 76 - DM2 ,

2 auxiliary logical nodes 48

connected to the corresponding inputs of node 46. The second channel is an auxiliary 52, the input of which is connected to the output S of the pulse width modulator 49 and element 2-2I-OR 53, the remaining inputs of which are connected to the outputs of the first 1K flip-flop 38 and pulse width modulator 49. The output I of the auxiliary node 48 connected to the corresponding inputs of the node 47 is provided with the realization of a logic function, S + Q, S. Node 48 is used when it is necessary to control the output voltage. Without using this node

the inputs of the nodes 46 and 47 forming the up-35. The pulses U.jC of its output are received by equalizing signals by the modulus keys. The inputs of the frequency dividers 33 and 34, denoted respectively by F and the division factors of which are connected by I, are connected directly to N and N 1 1. I-lMeHHO in this moves of the first and second 1K-flip-flops, the case on the comparison circuit 2I-HE 35 so that F Q and I Q. . 40 there are pulses, the frequency of node 46 is made in the form of three identifiers equal to 12 f g ,,, where there are real channels, each of which with the first output voltage frequency holds four ZI 54-65 elements, the converter. After dividing by 4 elements 4ШШ 66-68 and sequentially using the second divider for 36 hours, the element 69-71 connected to it is NOT. The 45th sequence of chips between the inputs of the logic node U, goes to the first input of the distributor and the corresponding outputs of the six-splitter 37 pulses. 34-channel distributor dividers 37 pulse-36 frequencies form narrow pulses

(U34 ts) of exclusion of the state of the ambiguity scientific research institute inherent in IC triggers, and thereby increasing the functional reliability of the device as a whole, the distributor 37 for 1–1 pulses is made according to the scheme described above. For 55 of the same purpose, a set of narrow pulses Ujj is supplied to the setup input I of the first 1K-trigger 38, and the sequence Pe is fed to the setup input I of the second IK-flip-flop 39.

owls provide the implementation of the following logical functions: at the output of the ZI element 54 - 55 -, Q g, 56 -, 57 -. Ha of the output of element 4IL 66 a signal Ml Q is formed. Q, Q, Qg + FQ Q, -H, a at the output of the logical element HE 69 is the signal Ml. The remaining channels are made similarly and form the signal M2 Q iQ tQ 8 + Q iQ frQ g Q 8 + FQ bQ «on the outputs of the OR 67 element; Element 70 - M2 signal, -71 - MV. The outputs of node 46 are connected via an amplifier.

Develop a node with control inputs Ml, Ml - MH, MH of keys 2-7 of modulator 1.

Node 47 is also made three-channel. Each channel consists of a 2-2I-OR 72-74 element in series and a NOT 75- 77 element. Connected to the distributor 37 pulses, nepBbw 1K-trigger 38 and

auxiliary logic node 4B

77 - DMZ. The outputs of node 47 are also connected via an amplifier and expansion node with control inputs DM1,

DM1-DMZ, DMZ keys 22-27 demodulators 19-21.

The principle of operation of the proposed device for controlling the converter is explained by the timing diagrams presented in Fig. 3.4c. Consider the principle of generating control signals by the keys of the converter (Fig. 3). The gadget generator 32 synchronizes the operation of the device.

In this case, the outputs of these triggers also ensure stable formation of sequences of pulses Ujg, Ugg, and in

if necessary (random failure, etc.), each / 6 period of the output frequency trigger 39 and every 1/12 period fgj, trigger 38 are automatically forcibly reset. The pulse width modulator 49 provides, in accordance with the signal, the formation of a sequence of pulses, the duty cycle of which can vary from 0 to. Nodes 46-48 are executed on standard microcircuits, I perform the C1d: well-known logical operations. The signals at some of their outputs are shown in FIG. The numbers of the signal sequences correspond to the numbers of the microcircuits.

A feature of the construction of modulus 1 p is the use of a common rack of keys 8.9 for the formation of modulated voltages U, - U,. of all three phases A, B C, To control inputs M 4, M4 of keys 8.9 send control signals Ujg, U () (FIG. 3) with constant frequency. To control inputs Ml, Ml - MZ, MZ of keys 2- 7 remaining racks of the modulator 1 control signals are supplied with a greater or equal frequency (unlike the prototype, where the control signal is supplied with a greater, equal and lower frequency, which unnecessarily complicates the structure of the control unit) at angles of control 0 or 0 a signal of type F and a signal of equal frequency (U,., and 3 in FIG. 3) with 0 at the corresponding conductivity intervals due to required phase shift. The presence of the same switching frequency of the power switches 2–9 of the modulator 1 makes it possible to form on three power transformers 13–15 a variable high-frequency voltage of a rectangular shape (for example, in the interval / 6-5 / 6 (signal U, j in FIG. 4) The difference, the switching frequency of the keys 2-7 from the switching frequency of the keys 8-9 allows to form a variable modulated voltage at (for example, the signal U, j in the interval - / Y / 6 - 5 "76 and 5 fT / 6-7 / G / 6 in Fig. 5 or the voltage, the form of which is represented in Fig. 4 (at the same conductivity intervals). Such a form, eg 9 872b

This allows you to get three demodulators on one wire. 19-21 on a three-phase load connected in a star, three three-phase voltages with a single-pole PMM with a phase wave of 120 °

(и29 30 in figure 4, 5).

By comparing the spectral composition of the phase voltage in the proposed device and in the prototype, it can be noted that the relative magnitude of the main harmonic increases by 14.8% (Uj 1.218 P ;,, kg compared to Uj, 1.061 prototype), and this is achieved with the same number switching power switch keys (). At the same time, the quality of the converted electricity is doubled (K (i) is reduced from 0.41 to 0.21 (Fig. 6).

Claims (1)

Invention Formula Device for controlling a constant-voltage three-phase quasi-sinusoidal converter, including a modulator in the form of four key racks with control inputs Ml, Ml - M4, M4, connected between the power buses, three single-phase transformers, one ends of the primary windings of which are connected respectively to the points connectors of keys of the first three racks, the other ends of these windings are combined and connected to the point of connection of keys of the fourth rack, three single-phase demodulators on the AC switches with control inputs D M1, DM1 - DMZ, DMZ, connected to the secondary windings of the corresponding transformers, with one of the same type demodulator circuits combined, others are output terminals tel containing a frequency adjuster connected to the first frequency divider, the output of which is also connected to the second integrity divider, the output of which is connected to the first input of the distributor, pulses, the third frequency divider and the driver of the control signals by the modulator keys, the inputs connected to the outputs of the pulse distributor The outputs are intended for connection to the equal inputs Ml, Ml - MH, MZ of the keys of the first three racks of the modulator, characterized in that, in order to improve the quality of the electric energy bath by increasing the content of the main harmonic and reducing the coefficient of voltage and current harmonics; it is equipped with two 1K-triggers with paraphase outputs Q, Q and Qj, Q, j, element 2И-НЕ and the driver of the control signals with demodulator keys, the inputs of the pulse distributor and the first 1K flip-flop connected to the outputs, the output of the first frequency divider is connected to the second splitter via the first input of the 2I-NO element and the counting input of the first 1K flip-flop, the second input of the 2I-NOT element is connected to the output of the third divider frequency and is connected to the counting input of the second 1K-flip-flop, and the output is connected to the installation 1-input of the first 1K-flip-flop, intended to connect the code to the control inputs of the keys of the fourth rack of the modulator, so that, M4 Q1, the input of the third frequency divider is connected to the output of the frequency sensor, and the pulse distributor is made of a channel-channel with paraphase outputs Q3, Q Qj QS 0 five 0 on a scaling circuit with cross-links on the three main 1K-trigger-, pax, counting inputs — which are connected to the first input of the distributor — the outputs QgjQj Qj, Qj- to the installation inputs of three additional IK-triggers, the counting inputs of which are combined The second additional input of the pulse distributor connected to the output of element 2И-НЕ, and the connections to the circuit of the outputs of the 1K-flip-flops, the distributor of pulses and the outputs of the control signaling drivers are implemented with the following logic functions: Ml Q, Q, Q, + Q, Q, Q, + Q2 Q.Qe + ,, M2 Q, Q, Qg +, + Q, Q, Qe + Q, Q, Qe; M3 + Q, Q, Q, + Q., l DM1 Q, Q3 + Q, DM2 Q, Qj + Q,. DAZ Q, Q Q, Q ,, a first, second and third dividers, 5 frequencies are made forming narrow output pulses and with division factors N, 2, Nil, respectively, where N is any integer number. Jff If9 figure 1 28 cpus.Z m sh one I AND ait I I ffl oJf , fS 6 and.  29 Ljt Psh and ) J and.  28 and.  29 shs ± 1G and,  L About : IL IL Tt 632.3S FIG. five iniUL F (Jt O 5 S 15 W FIG. 6