SU1285600A2 - Analog-to-digital converter with frequency conversion - Google Patents

Abstract

The invention relates to a pulse technique, in particular, voltage-to-digital voltage transducers with intermediate voltage-frequency conversion of 1 pulses, and can be used in precision analog information acquisition devices of process control and management systems. Into a device containing a voltage converter 8 to a pulse frequency with an input switch 7, a subtractor 17 with an analog input key 16, three counters 3, 19, 6, two triggers 4, 5, elements 12-15 AND and OR 11, single-oscillator 2 and the reference frequency generator 10, in order to increase the accuracy of the converter by reducing the effect on the result of converting interference from the industrial network when its frequency changes, synchronization and correction blocks 23, 24, a zero-body 22, a driver 25 pulses and element 26 OR are introduced . 2 hp f-ly, 4 ill. (L

Description

The invention relates to a pulse technique, in particular to voltage converters to a digital code with an intermediate conversion to a pulse frequency, and is an improvement of the device according to the author. St. No. 1150769.

The purpose of the invention is to improve accuracy.

FIG. 1 shows a block diagram of the device; in fig. 2 is a block diagram of a synchronization unit; in fig. 3 is a block diagram of a correction unit; in fig. 4 - time diagram of the device.

The ADC contains bus 1 to start it up, one-shot 2 damping, first counter 3, trigger 4 cycles, trigger 5 cycles, reversing counter 6, analog switch 7, voltage to frequency converter 8 (IFF), input bus

9g of generated signal, generator

10 of the reference frequency, the first element OR 11, the elements AND 12-15, the analog switch 16, the subtractor 17, the reference voltage bus 18, the second counter 19, the output results 20 buses of the conversion result code, the input bus 21 of the supply voltage, zero the body 22, the synchronization unit 23, the correction unit 24, the pulse shaper 25, the second element OR 26,

The synchronization unit 23 comprises a subtracting counter 27, an output register 28, a one-shot 29, an AND element 30, an IL 31 element, and a pulse shaper 32.

The correction block 2A contains the first counter 33, the decoder 34, the second counter 35, the trigger 36, the pulse shaper 37, the one-shot 38, the first 39 and the second 40 elements And, the elements 41, 42.0.43 of the group, the first 44 and the second 45 elements of the RSHI.

The timing diagram (Fig. 4) indicates: a pulse 46 for starting the device into operation, output pulses 47 of the null organ 22, 48 — the time of operation of the counter 27 for determining n, pulses 49 of recording n into the counter 19, signals 50, 51, 52 Accordingly on you

course 1

trigger trigger

1 cycle trigger and the output O of the high bit of counter 19, the signals 53 and .54 of the on state of the elements 12 and 14, the pulse 55 of the counter overflow 3, the signal 56 is turned on5

O 5

0

five

0

0

key 16, time 57 connection to the FSI 8 of the reference voltage, the signal 58 of the code O in the counter 6, the signals 59 of the counter 35 when summing n pulses 60 correction of the conversion result, the signal 61 at the output 1 of the trigger 36.

The device works as follows.

Using a null organ 22, pulses 47 are formed from the voltage of the mains supply removed from bus 21, at the time it passes through zero, which in block 23 obtains the number n. This is done by counter 27, in which pulses from generator 10 are subtracted after resetting it in O by pulses 47. Therefore, the occurrence of the next pulse 47 in the counter 27

the number n N y T f .. is formed, which is written to the register 28 by this pulse, then the signal from the output, the former 32 sets the code O in the Counter 27 and the subtraction of the pulses from the generator 10 continues for the time 48 of the next cycle to get a new value counter 27 is significantly reduced compared to N., since by the end of each cycle, code n remains and P bits are required, the number of which corresponds to the maximum value of n, "a few percent of NQ for the considered

cases of change of Tf ,.

I

In block 23, a circuit of AND 30, a single vibrator 29, and an OR 31 element is inserted to ensure that an invalid code is not written to the register 28 when subtraction and transients occur in counter 27 at the time of coincidence. pulses 47 and generator 10. In this case the moment of writing the code with the help of the one-shot 29 is shifted by the end time of this transient process,

The resulting code n is used to reduce T ", which is executed twice (pulses 47) on start pulse 46 and after the first half of Tfip has ended on a negative differential signal 52 using a former 25. Negative differences of these pulses write the code n in counter 19, which is installed

312856004

Therefore, the switching code of the 2Uo-Ujj extension, connected to the input of the th digit of this counter (signal 52,), the IFA 8 with a switch. 7, since

defining time -r- T happens

2 pr

one

twice in time () -, and

em transform TJ equals T „p

 2 (11 -p) 1- "

signal 50 is zero. In addition, the signal from the output O of the trigger 5 switches on the subtraction mode in the counter, 6, and the pulses from the LIF 8 in it reduce N.

For time T in the counter 6 act

With the arrival of a pulse 46, the one-shot 2 resets counters 3, 6, 19, and 35 to O, then sets to trigger 5 and writes the code n to counters 3 and 19, the first half of Tp begins, during which the signal 50 s Output 1 of the trigger 5 is connected via a switch 7 U to the input of the FSP 8. Its output pulses are counted by counters 6 and 3, in

the elements AND 13 and OR 11 from the generator 10 receives the number of pulses Xf,

the last of which they double, 20 as many of them arrive in block 24.

If by the end of T uN O, then the third T stroke of the conversion is performed, in which the removal of the signal from the output of the high bit of the counter 19

c, since they arrive through the element I 12 (signal 53) to the input of the second

younger bit In time

counters 6 and 3 receive the number im- 25 prohibits the operation of the element I 15. pulses N, (Wg-n) -. On account of Chick 6, the code N ,,, and in

the counter 3 receives the code X (, (2N ,, + п) X, + Po The last of them is used to determine the end time of the first clock cycle T, for which from the second half T ol into the counter 3 through the element 14 (signal 54) and the element OR 11, pulses are received from generator 10, which increase the code X, and at the moment of overfilling of the counter 3 T (ends. During this time, the number of pulses N,

 (X, + n) J - which

is matched with AND "and forms the code N (N,

counter 3 sets a trigger 5 to O and a trigger 4 to 1. From this moment on, the second conversion cycle begins. Its duration is equal to:

T, Tpr - T, 2 (N, -n) f- 1, „V 1

- l,

+ N, 2 Pulse 55 overflow

MP .. Хр:, () - U.X, including a key 16. The output of the subtractor is set to a voltage of 2 U ,, (signal 57), which is converted by the FNC 8 to impulses that compensate for DD

30 to zero. When uN O, the decoder of the code O of the counter 6 signals the 58 signal of the end of the TK and the conversion, which sets the trigger on O. During the time T, the number of pulses N, 2 S-x goes to counter 6

X X, ---, in counter 3 from the generator

ten

10, elements AND 13 and OR 11 receive X pulses, which form the code Xp X + X there, and block 24 also receives X pulses.

From the equation uN N, - N N3. It is possible to determine the code in the counter 3

one

one

 2 f

. 2 4G- or U), (N -n) Uo (X, +

-k + X) Uo-Xp, whence Xp (N, - (X, 4-n) l

with -

one

- - (NO-П) -, r- - -, ..

--o J-o- O

During this time, the signal 51 from the output 1 of the trigger 4 allows

50

-)five( -.§;).

work elements And 15, 13 and block

The number of pulses XP enters block 24, where N pulses are generated, transmitted through the element OR 11 to the input of counter 3, correcting 24. The output signal of element 56 and 15, 55 is its code: X. Хр N., entering the control input of the key Allowing block 24 to work, signal 16 connects U to subtractor 17, 51, the opening element AND 40 for the output of which is formed, for example, the passage of Xy circuits with output 1

2Uo-Ujj, connected to the input of the FNC 8 switch. 7, since

signal 50 is zero. In this case, the signal from the output O of the trigger 5 switches on the subtraction mode in the counter, 6, and the pulses from the LIF 8 in it reduce N.

During the time T in the counter 6 enters

number of pulses Ng (2U (| -U) SX

0

and there remains in it the difference: dN N, -N, or Li „-n) S i + U, (X, -« + n) S. 1- - (,) SX, 1-, (N --- o

-n) -, S -.

o For the same time in counter 3 through

the elements AND 13 and OR 11 from the generator 10 receives the number of pulses Xf,

as many of them arrive in block 24.

Хр:, () - U.X, including a switch 16. The output of the subtractor is set to a voltage of 2 U ,, (signal 57), which is converted by the FNC 8 to pulses that compensate for DD

to zero. When uN O, the decoder of the code O of the counter 6 outputs the signal 58 for the end of the Ts and the conversion, which sets the trigger to O. During the time T, the number of pulses N, 2 S-x is sent to the counter 6 from the IF 8.

X X, ---, in counter 3 from the generator

ten

10 through the elements of AND 13 and OR 11 receives X pulses, which form the code Xp X + X there, in block 24 also receives X pulses.

From the equation uN N, - N N3, you can determine the code in the counter 3

one

 Xp:, () - U.X, i1

 2 f

. 2 4G- or U), (N -n) Uo (X, +

+ X) Uo-Xp, whence Xp (N, 50

-)five( -.§;).

element AND 1,3, With the arrival of each of these pulses, the counter code 33 is increased by one and starts- shaper 37, the output pulse of which passes through the element AND 39 opened by the signal from element OR 45 when there is a code different from O in the counter 33, and starts the one-shot 38. Its output signal, similar to the input signal, repeats the operation of the driver 37 and the one-shot 38. The number of these cycles is determined by the capacity of the counter 33, which must be at least (P + 1), and for code O, the nodes cease until the appearance new impetus to Xn.

At the output of the decoder 34 form-. sequence of pulses arriving at the elements And 41, 42,., .., connected to the counting inputs P of the lower bits of the counter 35. Depending on the presence of signals 1 in the bits of the input code with the value of n in the counter 35, a random summation (signal 59), and its code will be increased. After the arrival of all the pulses Xp in the counter 35, the value Xp should be obtained. Since the capacity of the counter 35 is equal to N (, then the result is NI, impulses of its overflow and in its bits the code may remain

HS

those.

XP-N.

N,

+ m

j, i.e. Lr and Eid UK,. whether

When each overflow pulse 60 occurs, it is remembered by trigger 36, the output signal 61 of which, passing through Element OR 45, allows the one-shot 38 to start with the O code in counter 33. Due to this, counter code 35 is incremented by n NK.

The maximum value of Wj, corresponding to Xp NQ, is equal to n, therefore the maximum increase in the code is equal to n, and Ni /, j overflow pulses of the counter 35 can arise from it only if. In the device in question, as shown above, the change is 4% and n:

 i4% Ko, therefore N, 2.5 x

X 10, and only with Ng 2500, an N overflow may occur. Taking into account that in the counter 35. the code tp remains, when summing with it n-N, the value m, NO-NK + m is obtained.

:( + nN

can

K1

12856006

In this case, an additional summation will be performed with obtaining the value: П N, + m, j KgNj + m. For the condition xp n,. even at 5 maximum conversion result, the value (n-N ,, + m), which; remains in the counter 35, does not exceed N and the further mathematical description of the operation of this counter) 0 is not required.

The number of output pulses 60 blagaz 24 N is equal to:

Tl N + N + N. KI 2 K3

 5 From the above expressions can be represented:

- p | EL N N, S + EL ™ L,

   And w „N /

20

... t: st

Si

NO

Substituting these values in N, we get:

1m ilL Il. + IL.} 12d21 h NK - Xp (j – j. (M „-

+ + EB.) V. Nn

   p Vi, - 11.

The NI pulses go to counter 3, where they are summed up with the Xp code accumulated there, and the final result of the transformation is obtained: Xk Xr +

+ X

R

N

K (1

- N ,,, X (1 - n) (+

h-11

..ki) -NK ,,

 X - X

I

N

- NK ,,

in this expression, for the case under consideration, the ratio pn N, the second term is negligible, a.

is a fractional part that remains in the counter 35 and is a value less than one, i.e. Xc X + X, where X§ «1.

5 The result X ,, is obtained during the execution of the second T and, EC; this is necessary when the AH 7 O, the third Td-cycles of the device operation. No additional time is required to perform the Xp correction.

The proposed device allows to increase the accuracy by reducing the error that occurs when the frequency of the noise changes.

Claims (3)

Invention Formula one . .Analog-digital converter with frequency conversion by auth. St. No. 1150769, characterized in that, in order to improve accuracy, a null organ is added to it, the input of which is connected to the power supply bus, synchronization and correction blocks, pulse shaper, the second OR element, the output of which is connected to the recording input the second counter, the first input is connected to the output of the pulse former, the input of which is connected to the zero output of the senior bit of the second counter, the low-end inputs of which are combined with the same inputs of the first counter and the information inputs of the The inputs are connected to the corresponding outputs of the synchronization unit; the reset input of the correction unit is combined with the recording input of the first counter and the second input of the second OR element and connected to the output of the one-off damper; the enable input of the correction unit is connected to the cycle trigger output; is connected to the output of the second element, And, and the output is connected to the third input of the first element OR, the counting input of the synchronization unit is connected to the output of the reference frequency generator, and the clock input is connected to the output of the zero-organ. 2. The converter according to claim 1, characterized in that the synchronization unit is executed on a subtractive counter, the outputs of which are connected to the corresponding information inputs of the register, whose outputs are the outputs of the synchronization unit, and the recording input is combined with the input of the pulse builder and connected to the output of the OR element, the first input of which is connected to the output of the one-shot, the second. The input is combined with the first input of the AND element and is a clock input of the synchronization block, counting O 0 5 0 5 five the input of which is the second input of the element And, combined with the counting input of the subtracting counter, the reset input of which is connected to the output of the pulse former, the output of the element And is connected to the input of the one-oscillator. 3. The converter according to claim 1, characterized in that the correction unit comprises a first counter, the counting input of which is combined with the input of the pulse former and connected to the output of the first OR element, the first input of which is connected to the output of the one-vibrator, whose input is connected to the output of the first element And, the first input of which is connected to the output of the pulse former, and the second input is connected to the output of the second OR element, the first input of which is connected to the single output of the trigger, and the remaining inputs are combined with the inputs of the decoder and Connected respectively with the unit outputs of the bits of the first counter, the second INPUT of the first element OR is connected to the output of the second element AND, the first and second inputs of which are respectively the counting input and the input of the correction block, the outputs of the decoder from first to P, where P is the number of information inputs of the correction unit connected to the first inputs of the elements AND of a group are connected respectively to the second inputs of the elements of the AND group, the outputs of which are connected to the inputs of the corresponding bits of the second counter , Which is reset, input correction unit odnoimenshm input (P + 1) th output of the decoder is connected to the zero input of flip-flop unit the input of which is connected to the output of the second counter overflows and is output correction unit. FIG. H