SU1282326A1 - Parallel-sequential analog-to-digital converter - Google Patents

Abstract

The invention relates to computing and measuring technology. The aim of the invention is to improve the accuracy and simplification of the converter. The second signal recorded in the device 2 by the signal of the control unit 21 is fed to the input of the digital amplitude analyzer (DAC) 3 and through the drivers of 8.9 difference

Description

ND

00

to

with you

ai

(rig 1 gz

fvp

signal - to the inputs of the CAA 4.5, respectively. The higher-order output code is generated on buses 22 using encoders 10, 13 and switch 15, which sends a code to the output, either corrected using correction correction block 18 or uncorrected with a compensating signal generated by the DAC 19, to the driver 8, the difference signal of which is analyzed in 11DA 4 and through the block OR 6, the encoders 11, 14 and the switch 17 are fed in corrected or unchanged to the medium size output bus 23. The code of the lower bits is formed by analyzing the difference signal generator 9 in DAC 5 and then encoded in encoder 12, the differential signal in driver 9 is formed from the input signal and the compensation signal formed by the DAC 20, the outputs of which receive codes from the first (through the switch 16) and second (from the encoder 11) stages Processing If necessary, adjusting the output codes of the high bits is carried out through the transfer of the signal from the output of the DAC 5, 1 Cp. 3 il.

one

 The invention relates to computing and measuring technology and can be used in the construction of analog signal converters to a diff code.

The purpose of the invention is to improve the accuracy and simplify the converter by parallelizing the operation of the second less accurate and the third more TOCCH conversion stages with a reduced number of analog blocks and the implementation of end-to-end transfer while correcting the conversion result.

The following is a structural electrical circuit of a parallel-to-analogue-diffractor converter (ADC), figure 2 shows a structural electrical circuit of a node including a second digital amplitude analyzer (DAC), an OR block and a second and five-pin coders, and its connection to the input block the corrections and to the third switch, in FIG. 3, are diagrams of reference levels of three conversion bits.

The designations adopted in FIG. 3: V. I is the reference level of the first CAA; .. - reference damage

   pl l ° oh

NO second CAA with a bit depth of 2,

where v

V - calculated

about

levels that correspond to the compensating voltage of the second DAC,

aV, is the magnitude of the preliminary displacement of the reference levels of the comparators of the first CAA .; dV, - pred5 value

five

.

l /

15

0

five

the reference levels of the second CAA relative to the calculated levels j & t, kt and At., is the time interval in which the input voltage V exceeds the reference

ON

the level of the third CAA, where m is its width,

Parallel-serial ADC contains the Bodnuro bus 15 analog storage device (AMS) 2, the first 3, the second 4 and the third 5 DAC, the first and second blocks OR 6 and 7, the first and second drivers 8 and 9 of the difference signal (FRS), PervA 10, second 11, third 12, fourth 13 and fifth 14 encoders, first 15, second 16 and third 17 switches, correction input block 18, first and second 1Ш1 19 and 20, control block 21 (БУ), output buses 22 older bits, output tires 23 bits, output tires 24 lower bits.

The first CAA 3 includes outputs 25 and 26, the second CAA 4 includes outputs 27-31, the third CAA 5. includes outputs 32-34, block 18 includes inputs 35-37, and also contains the element OR 38 and element 39. The control unit 21 includes outputs 40-43 and reset bus 44, and also contains a pulse generator 45, a pulse distributor 46, a trigger 47 and drivers 48-50 pulses. The second CAA 4 contains (Fig. 2) comparators (K) 51-55, the elements EXCLUSIVE OR 56-62. Block OR 6 contains the elements OR NOT 63-66. The encoders 11 and 15 contain the elements AND-HE67-74

A parallel-serial ADC operation is as follows.

When a reset pulse is applied to the reset shknah 44, the distributor 46 is set to its initial state at which a logical O is set at its first output, which leads to the establishment of a flip-flop 47 at the output and, therefore, the logical output 1 of the first output 40 of the block 21 storing the input signal V. (t), incoming

on input bus 1 for the duration of the logical signal at output 40, i.e. until, under the action of the clock pulses that arrive from the output of the generator 45 to the input of the shift, the logical O signal arrives at the second input of the distributor 46, which will cause the flip-flop of the trigger 47 to another state. In this case, the logical O in the distributor 46 under the action of the generator 45 will sequentially flow (with corresponding intervals of time, which depend on the number of intermediate transitions inside the distributor 46) to the inputs of the formers 48-50, which, in turn, will form at the outputs 41- 43 BU 21 short high-level pulses, thereby realizing the time synchronization of the work of the CAA 3-5.

After recording the input signal

At „(t) in the CCD 2 this signal is received

lx to the first inputs of the formers 8 and

9, as well as to the analog input of the first CAA 3, where it is compared with the reference voltages and after the gate signal is output from the output 41 of the CU 21, the position code 11 ... 101 ... 11 is formed at the outputs 26, where O corresponds to the last of the comparators that have worked, and the inverse output of the first comparator is set to logical 1 or logical O.

Logic 1 is set at output 25 whenever the information logic O is present at outputs 26. This allows, taking into account the connection of the fourth encoder TZ to outputs 26 shifted by one input, to generate a binary code at the outputs of the first encoder 10

five

0

which is proportional to the position code of the first IIAA 3, and at the output of the even encoder 13 is a binary code, incremented by a low-order bit. This enables the subsequent selection of the output code corresponding to the code of the higher bits of the converter, depending on the presence of an error when analyzing the output signal of the AMS 2 by the first CAA 3. In this case, the presence of an error is revealed during the subsequent analysis of the output signal of the AMS 2 taking into account the result CAA 3.

It should be noted that the error probability exists in almost any analyzers, and for the unambiguity of these errors, each of the reference levels V (fig. 3) of the first CAA 3 is shifted by the value V relative to the calculated levels V, thereby specifying the sign of the error, and the correction errors are made by the first switch 15, which, depending on the logical level at its control input, passes to the output buses 22 either the HOP output code of the first encoder 10, or the output code of the fourth digit increased by one low-order bit rtogo encoder 13, simultaneously dvoichnsh first code encoder 10 is input to the first DAC 19, the output koto- 5 cerned formed compensating signal proportional to the result of the first conversion CAA 3. This compensation signal is supplied to the second input of the first driver 8, the output of which is formed

five

0

0

The first difference signal uV, which is fed to the analog input of the second CAA 4. When a pulse 21 is output from the output 42 of the block 21 to the gating input of the second CAA 4, position codes 000 ... 010 .. .00 are formed at its outputs 27 and 30 where the information signal is logical 1, and at outputs 28, 29 and 31 logical levels are formed in accordance with table 1 (the n-resolution of the AAC).

The positional codes of the high level from the outputs of the second CAA 4, the passage of the first block OR 6 and inverted therein, go to the inputs of the second encoder 11, where they are converted into a duplicate code, and to the inputs of the fifth encoder 14, where they are also converted to binary code, but at the same time increased by the unit of the youngest bit.

Let us consider in more detail the process of converting the first differential

remote control signal

6X1

From the release of the first

shaper 8 differential signal dU is supplied (figure 2) to the first inputs of the comparators 51-55, the second inputs of which are supplied with reference voltages V - shifted by

Vj, (fng.Z), the value of AV, 2 relative to the calculated levels V ... V

COP (S8

to eliminate the ambiguity of the analysis error of the second CAA 4. At the feed from the third output 42 of the gate signal unit 21, unitary codes are generated at the outputs of the comparators 51-53 and at the outputs of the comparators 54 and 55, which by means of the EXCLUSIVE OR elements 56-62 are converted into positional high level codes arriving at outputs 27 to 30 of the second CAA 4. Then, from outputs 27 and 30, the positional high level codes arrive at the corresponding inputs of the elements OR-NE 63-66 of block OR 6, where the high-level information code converts, B in the position code low level. Further, the code is fed to the inputs of the second encoder 11, in which it is converted into binary code by means of AND-NE 67-70 elements, and also to the inputs of fifth encoder 14, in which by means of AND-NE elements 71-74 is transformed into yes binary code.

An incremental binary code is generated by the fact that the inputs of the AND-NOT elements 71-74 of the fifth encoder 14, in accordance with the binary system, are connected to the outputs of elements SH-NOT 63-66 of the block OR 6, for example, if the first input The element AND-NE 67 was connected to the output of the element OR-NOT (code 0001, then the first input of the element AND-HE 72 is connected to the output of this element, thereby forming the code 0010, etc.

In the event that the first differential signal is LU „,. (figure 2) does not exceed

Wat

the reference level V of the comparator 52, then this means that there was no error in the code definition by the first CAA 3 and a logical one will be present at the output 28. O, which does not cause the appearance of logical 1 at the output of block 18,

In case the differential signal

falls into range

V ...

 V

1S

five

0

five

then at the output 28 of the comparator 52 a logical 1 is formed, which is fed to the second input 36 of the block 18, while not providing the operation of the AND 39 element, which is necessary for carrying out the end-to-end transfer, if the error value of the first CM 3 does not exceed the level of the preliminary displacement distance DU ( FIG. 3).

If uV V, then at output 29 of the comparator 53 a logical 1 appears, which goes to the first input 35 of the unit 18, passes the OR 38 element (figure 1) and supplies the output bus of the fourth encoder 13 to the output buses, and It also supplies the inputs of the higher bits of the second DAC 20 with the output code of the fourth encoder 13, which is incremented by a unit of the lower order bits.

During the conversion, the code from the output of the second encoder 11 through the third switch 17 is fed to the output buses 23 of the average bits of the converter, as well as to the inputs of the lower bits of the second DAC 20. As a result, a second compensating signal is formed at the output of the second DAC 20 which enters the second input of the second shaper, which leads to the formation of the second difference signal uVg, arriving at the analog input of the third CAA 5. When a strobe pulse is applied from the fourth output 43 of the BU21 to the gate input of the third CAA 5, at the outputs 32 and 33, unitary codes are generated, which, passing the second block OR 7 and the third encoder 12, are received in the form of a binary code on the output buses of the lower 24 bits of the converter.

In case the differential signal

0

50

55

 did not exceed the reference level of the th comparator of the third CAA 5, then the conversion result of the first and second CAA is not adjusted.

In case pink signal

 exceeded the reference level of the th comparator of the third CAA 5 (FIG. 3, ut and At), then the logical

1. From the output 34 (Fig. 1), it is fed to the control input of the third switch 17, applying to the output buses 23 an increased code from the output of the fifth encoder 14.

In the case (fig.Z, bt.), When it is necessary to carry out end-to-end transfer (it is always necessary, if logical 1 is present at the second input 36 of block 18), the element 39 and the output of block 18 are triggered by the signal from the output 34 of the third CAA 5 the signal arrives at the control input of the first switch 15, and an increased code is set on the output buses 22.

Claims (2)

1. A parallel-serial analog-to-digital converter containing an analog storage device whose information input is an input bus and the output connected to the first input of the first digital amplitude analyzer i, the first inputs of which are connected via the first encoder to the corresponding inputs of the first digital . analog converter, the output of which is connected to the first input of the first shaper of the difference signal, the output of which is connected to the first input of the second digital am10 15 It is connected to the second input of the first digital amplitude analyzer, the second output of which is connected to the first input of the fourth encoder, the remaining inputs of which are connected to the corresponding first outputs of the first digital amplitude analyzer, the first inputs of the first switch are combined with the corresponding first inputs of the second switch and are respectively connected to the outputs of the fourth encoder, the outputs of the first switch are the corresponding output buses of the higher bits, the second inputs of the first mutator combined with the corresponding second inputs of the second switch and respectively connected to the outputs of the first encoder, the third input of the first switch connected to the output of the input block corrections, the first input of which is combined with the third input of the second switch and connected to the first output of the second digital amplitude analyzer, the second output connected to the second input of the input block of the amendment, the third input of which is combined with the first input of the third switch and connected to the first output of the third digital signal amplitude analyzer, second and third outputs of the second unit through which elements are respectively connected in OR 20 25 thirty a secondary analyzer, and a second input to the inputs of the third encoder, and it is interconnected with the first input of the second differential driver and connected to the output of an analog storage device, the third digital amplitude analyzer, the first input of which is connected to the output of the second differential driver, the second encoder, whose outputs are connected with the corresponding low-order bits of the second digital-to-analog converter, the correction input block and the third encoder, whose outputs are corresponding to Downstream junior bits, characterized in that, in order to increase accuracy in operation, the fourth and fifth encoders, the first and second blocks of the OR elements, the first, second and third switches and the control unit, the first output of which is connected to the control analog storage device, and the second output . ten 15 2823268 Key to the second input of the first digital amplitude analyzer, the second output of which is connected to the first input of the fourth encoder, the remaining inputs of which are connected to the corresponding first outputs of the first digital amplitude analyzer, while the first inputs of the first switch are combined with the corresponding first inputs of the second switch and are respectively connected to the outputs the fourth encoder, the outputs of the first switch are the corresponding output buses of the higher bits, the second inputs of the first terminal mutator combined with the corresponding second inputs of the second switch and respectively connected to the outputs of the first encoder, the third input of the first switch connected to the output of the input block corrections, the first input of which is combined with the third input of the second switch and connected to the first output of the second digital amplitude analyzer, the second output connected to the second input of the input block of the amendment, the third input of which is combined with the first input of the third switch and connected to the first output of the third digital signal amplitude analyzer, second and third outputs of the second unit through which elements are respectively connected in OR 20 25 thirty 0 five The input is connected to the third output of the control unit, the quarter output of which is connected to the second input of the second digital amplitude analyzer, the third and fourth outputs of which are connected to the corresponding inputs of the first block of OR elements, and the fifth output connected to the first input of the fifth encoder, the second inputs respectively, combined with the inputs of the second encoder and connected to the corresponding outputs of the first block of the OR elements, and the outputs of the fifth encoder are respectively connected to the second inputs of the third switch torus, the outputs of which are the corresponding output bus of medium bits, and the third inputs are connected to the corresponding outputs of the second encoder, and the outputs of the second switch are respectively connected to the inputs of the higher bits of the second encryption module 91 go-Converter, the output of which is connected to the second input of the second driver differential signal. 2. The converter according to claim 1, wherein the control unit is configured on the pulse distributor, the trigger, the first, second and third pulse conditioners and the pulse generator, the output of which is connected to the first input distributor; pulses, second input 00 10 01 00 00 00 00 00 00 00  I 01 00 00 00 00 00 with S / JOKa 8 4 USx t g 82326 10 which is a reset bus, the first and second outputs are connected to the corresponding trigger inputs, the KOTopoi o output is the first output 5 of the control unit, the second, third and fourth outputs of which are respectively the outputs of the first, second and third pulse drivers, the inputs of which respectively connected to the third, fourth and fifth outputs of the pulse distributor. Sh Ltd about 1 1 1 Ltd 00 01 .. (2) IT2 ,  Pat's Auz ., (z) 1 / U3TS TsAAZ (g) U9T5 (2) Ustfy .. (Z) UyT3 (2) rogue ., (2) Uyri CAA CAA5 Ugx UKB fOOO --Uff7 Offf At: and kb 01 fo U, AA5 U8x UKS Offf / 2 ±: UK OfOO Ai2 and KZ 00ff UKZ uOio HAAS USx UKt ODOf