SU1277369A1 - Digital converter of pulse repetition frequency - Google Patents

Abstract

The invention can be used in automation devices, in radio receiving and transmitting devices, mainly in cases when high demands are placed on preserving the original phase stability and microminiaturization of devices. The purpose of the invention is to expand the functionality of the device. The converter contains a high-frequency pulse generator 1, bus 3 and 4 logic zero and control, respectively, an n-bit reversible counter of 5 pulses, bus 6 and 7 enable the add and subtract frequencies, respectively, converter 2 code-frequency, comparator 12, generator 13 sawtooth voltage and driver 15 pulses. Introduction of a code-voltage converter 11, a persistent storage device 9, and a high frequency bus 10 and the formation of new connections between the elements of the device allow expanding the range of input and output frequencies, pulse tracing and allow adjustment of the converter parameters at a variable high frequency . The use of the device in the synthesis equipment - parts allows reducing the switching time of frequencies, 3 sludge. with (L

Description

% g4

ff 7 "The invention relates to a pulsed technique and can be used in automation devices, for the sake of optional and occasional devices, in measuring equipment, in particular, of time-keeping converters, mainly in cases when the initial requirements are preserved. phase stability and microminiaturization of devices. The purpose of the invention is to expand the functionality by ensuring operability at a variable high frequency and at the upper limit of the range of output frequencies. FIG. 1 shows a structural electrical circuit of the device ;, FIG. 2 - timing diagrams explaining the principle of a linearly varying hold, where 2a - and the startup speed of the fast plow; 2b — fast and slow voltage saws; 2c per, core impulses (relative to the impetus to start a quick saw); Fig. 3 shows signal timing diagrams (Z - n input 14; ST - output converter 2, code - frequency; Sv, r - respectively at the inputs and output of comparator 12; Rear - output 16). The device contains a frequency generator of 1 pulses, a 2 code converter — a frequency, a bus 3 of a logical zero, a control bus 4, a n-bit reversing counter 5 and pulses, buses 6 and 7 for switching on modes of frequency subtraction, respectively, the first converter. Code 8 - direct, permanent recording device 9, Hiinu. 10 high frequency code, second converter 1 1 code - voltage, comparator 12, sawtooth generator 13, spacing input 14, driver. 15 pulses, output 16 of the device. The high-frequency generator of 1 pulses (Fig. 1.) is connected to the input of a clock, the converter of a frequency code 2, the inputs of which are with weights. 3 logical zeros are connected with the scales and 4 with the control bus 4, the n-bit reversing counter 5 pulses is connected by a counting input to the output of the 2 code-frequency converter, the first and second control 692 inputs are connected to 6 and 7 enable modes respectively. No frequencies and frequency subtraction, and the outputs are connected to the input of the first converter; the 8 code is voltage. The address input of the permanent storage device 9 is connected to the high frequency code bus 10, and the output to the input of the second code converter 11 is voltage. The first and second inputs of the comparator 12 are connected respectively to the outputs of the first converter 8 code — voltage and generator 13 of the sawtooth voltage, connected by the first and second inputs respectively to the output of the second converter 1I code — voltage and to device 14, and the output through shaper 15 pulses - with output 16 devices. Bus 3 logical zero is constantly fed zero potential. The control bus 4 is supplied with a code (for example, a binary one) corresponding to a low frequency F. Serving the frequency code F only to the input of the upper bits of the converter 2, the code giving the frequency when zeroes are preserved at the last n bits, is equivalent to multiplying the number F by a number. Therefore, in fact, the code NF is entered into the 2 code – frequency converter. Units 6 and 7 are used to enable the modes of addition and subtraction of frequencies, respectively. The first and second inputs of the sawtooth generator 13 serve to supply voltages of power supply and saw start pulses, respectively. In the permanent storage device 9, a binary code is written for each high (input) tracking frequency, corresponding to the voltage value of the generator 13 sawtooth voltage wives A binary code is sampled from the persistent storage device 9 by feeding to its address inputs via the bus 10 the binary code of the cell address in which the voltage value is written. corresponding to the frequency of following the INPUT of 1–1 pulse of the device. The Converter operates as follows. Before starting the device, a code corresponding to a low frequency F is set up on the control bus 4, and a high frequency code f on bus 10. The up / down counter 5 is zeroed.

On the bus 6 and 7, depending on the mode of operation of the device serves the required potentials. After starting the device, an input sequence 14 receives a sequence of pulses with a high frequency f of the following, which is converted into a sequence of pulses with a frequency fiF at output 16,

An offset of the high frequency f to the desired value is realized based on the principle of a linearly varying delay. Its essence lies in comparing the amplitude of two saw-tooth stresses — a fast saw and a slow PIPA (FIG. 26). Pulses delayed relative to the start pulses (FIG. 2a) and generated by the fast saws (FIG. 2c) are equal to the moment of equality of the stresses of the fast and slow saws. Moreover, if these sawtooth stresses or both increase or both decrease, the delay increases with time. If one of them increases and the other decreases, the delay decreases with time. This technique is used to provide a linearly increasing delay (offset to the delay side) of the device output pulses in the frequency subtraction mode (f-F), as well as a linearly decreasing delay (shift in the direction of advance) of the device output pulses in the frequency addition mode (f + F),

As it is shown with the help of diagrams in FIG. 2, the possibility of shifting the high frequency f downward, t, e, is, obtaining the frequency f-F. Let the period of the following start-up pulses (Fig 2A of the fast saw be equal to the period of the input pulses Tc with a high frequency f of the following, and the duration of the slow saw be equal to the period of the pulses with a low follow-up frequency (Fig 2, b). - installation (FIG. 2b), then delayed by jg ka will be equal to

T; i oo (o

where yC is the delay (offset) step; , 2 ,,,, t, „At) - the number of the pulse in the sequence"

start pulses (FIG. 2a) for a time interval equal to T ,,

As can be seen from FIG. 2c and formula (l), the range of variation of the delay is from dc to T. Thus, if in the initial sequence of start pulses (Fig 2a) for a time interval equal to i counts, then in the sequence of delayed pulses (FIG. 2c), i-1 pulses are now in the same time interval. This is due to the fact that the i-th pulse, as a result of the shift by the period Tg, has gone beyond the interval TC, Therefore, the frequency of the delayed pulse is shifted

pt-t "-l

vyffp

In a similar way, obtaining 7 for the case of frequency addition can be noted.

The voltage of the fast saw (fig, Sv) is generated by the sawtooth generator 13 in the pause between the input pulses coming from the input 14 of the device (Fig. 3a). These pulses reset the output voltage of the sawtooth 13 generator to zero, the voltage of the slow saw (fig, Sv) is generated by the first code 8 transducer - voltage. In order to get a slow saw,

0 in which the height does not depend on the period (frequency), an approximation of linearly varying voltage with a step voltage is applied. The number of Art; at any value of the period, the stub of approximation is the same and equals the number of states of the n-bit reversible counter of 5 pulses, the bit of which is equal to the size of the first converter 8

0 code - voltage, as well as the number of the best bits of the converter; 2 code frequency, to which a zero potential is constantly applied. Since the duration of the slow saw is determined by

5, the filling time of the p-bit reversible counter 5 (counting from the zero state), then to fill it during the time T ", pulses with a frequency NF (Fig. 3b) are required ,. 0 Indeed, the filling time of the counter 5 in this case version

equally

4 ion

 The task of forming a sequence of pulses with a following frequency NF is performed by the converter 2 code - frequency, which is clocked

the pulses of the high-frequency generator 1. Thus, the constancy of the number N of steps of the slow saw is ensured for any value of the period Tj ,. As can be seen from FIG. Sv, an elementary increment of a slow saw is equal to the height of one step

 , (.)

where Ug is the reference voltage of the first converter; 8 code is the voltage equal to the height of the slow saw.

The comparator 12 at the moment of equality of the stresses of the fast and slow saws (Fig. 3g) starts the shaper 15, from the output of which another pulse arrives at the output 16 of the device.

Consider the principle of operation of the device at a variable high frequency f. Its essence lies in the fact that, depending on the nominal input frequency to be set, the power supply voltage of the sawtooth generator 13 also changes. This is necessary so that the height of the fast saw is not dependent on the tracing period of the input pulses. If the sawtooth voltage is formed at a time interval equal to the period of the following impulses, then the height and, „of the fast saw is equal to

tm q.m (3)

Um-s

where S, EJLOJ are, respectively, the steepness, the supply voltage, and the time constant of the charge circuit of the sawtooth generator 13. As can be seen from formula (3), a constant of magnitude (with variable, often f) can be achieved by varying the supply voltage E at a constant value. We obtain from formula (3) the expression

E, -U tj-f. (4)

It can be seen from formula (4) that the value of E for each known nominal frequency f is determined. Consequently, using a permanent storage device 9 it is possible to store in it a binary code of the value E for all frequency ratings. The second transducer I1 code - voltage forms the voltage level E, according to its binary equivalent.

When the device is tuned to a high frequency, the code of the number of this frequency on bus 10 changes simultaneously with the change of the nominal input frequency f. As a result of this, the second converter 1 code-voltage forms a new voltage level E corresponding to the installed input frequency.

The pulse sequence at the output of the comparator 12 (Fig. 3g) is close to ideal, but differs from it by the presence of parasitic modulation of the phase of the output impulses. This difference is due to the fact that the slow saw is not perfectly linear, as in FIG. 26, and the step. Find the associated error of the temporal position of the output pulses of the device. From geometrical considerations in FIG. Sv can get equality t

p F - a

where, taking into account (2), we get

, T ,.

(5) j To estimate this error, let us set the values of Tj, and based on the capabilities of the modern elementary base. When implementing digital units of the device on a chip series 155, operating at frequencies up to 15 MHz, we take MHz. Then, 1 µs. The maximum number of bits in modern transducers, the code - voltage (572 series) is n "(, p 12. Substituting the selected values 1 and n into formula (5), we get

 "Ac 5 g - 2-10mks 0.02 no.

Claims (1)

Invention Formula A digital pulse frequency converter containing a high-frequency pulse generator, a logic zero bus, a control bus, a code-frequency converter, a clock input of which is connected to the output of a high-frequency pulse generator, the junior inputs have a logical zero bus, and the higher (qn) inputs are control bus, p-bit reversible pulse counter, the counting input of which is connected to the output of the converter code - frequency; the first converter code - voltage, the inputs of which are connected to the outputs of -dischargeable reversible pulse counter, a comparator, the first input of which is connected to the output of the first converter code - voltage, a saw-tooth generator, the output of which is connected to the second input of the comparator, a pulse driver, the input of which is connected to the output of the comparator, and the output is the output device, characterized in that, in order to expand the functional capabilities of the device by expanding the range of values of input and output pulse frequency oyki transducer parameters at variable high repetition rate, it entered code bus a high frequency, permanent storage device whose address input is connected to the high frequency code bus, a second converter code voltage, the input of which is connected to the output of the permanent memory device, and the output is connected to the first input of the sawtooth generator, the second input of which is the input the device, a bus for switching on modes of addition and subtraction of frequencies, connected respectively to the first and second control inputs of an n-bit reversible pulse counter. but / eight ZaG i-z ( 11-1) l G Phage.2