SU1330727A1 - Pulse-running frequency multiplier - Google Patents

Abstract

The invention can be used in digital frequency meters of low and medium frequencies with a wide range of changes in the frequency of input pulses, as well as digital control and regulation systems. The purpose of the invention is to expand the operating frequency range while maintaining accuracy - by introducing the third integrator 10 and the reference voltage unit 11 into the frequency multiplier. In addition, the frequency multiplier contains integrators 1 and 2, a sampling and storage unit 3, a comparator 4, a pulse shaper 5, an output bus 6, a control unit, an input bus 8, a source 9 of the reference voltage. Unit 11 contains a voltage source 12, which, through voltage divider 13, is connected to diodes 14 and 15. The multiplier has a high response speed, which ensures higher accuracy and expansion of the operating frequency range. 2 hp f-ly, 3 ill. w (L C CA GO 0ta.f

Description

The invention relates to a pulse technique, in particular to multipliers of the frequency of pulses, and can be used in digital frequency meters of low and medium frequencies with a wide range of variation of the frequency of input pulses, as well as digital control and regulation systems.

The purpose of the invention is to expand the output diameter of the control unit 7; - in the working frequency while maintaining accuracy.

Figure 1 shows the functional electrical multiplier circuit; Fig. 2 is a schematic of the voltage reference block, an example of the embodiment; 3 shows timing diagrams of the pulse frequency multiplier.

The pulse multiplying frequency multiplier contains the first 1 and second 2 integrators, sampling-storage unit 3, the input of which is connected to the output of the first integrator 1, and the output - with the first input of the comparator 4, the output of which is connected to the input of the pulse former 5, the output of which is connected to the clock the input of the second integrator 2 and the output bus 6. The input of the control unit 7 is connected to the input bus 8, and the first and second outputs are connected to the clock inputs of the integrator 1 and the sample-storage unit 3, respectively. The output of the source 9 of the reference voltage is connected to the first input of the third integrator 10, the second input of which is connected to the output of the sample-storage unit 3, the inputs of the first 1 and second 2 integrators are connected to the output of the reference voltage unit 11, the input of which is connected to the output of the third integrator 10 .

The reference voltage unit 11 contains a voltage source 12, the output of which is connected via the voltage divider 13 to the anode of the first diode 14, the cathode of which is connected to the output of the reference voltage block 11 and the cathode of the second diode 15, and the anode to the input of the block 11.

The reference voltage block 11 (FIG. 2) may contain reference voltage sources 16, the output of which is connected via an divider 17 to the anode of a diode 18, the cathode of which is connected to the output of block 11 and through series-connected first 19 and second 20 resistors to the input of block 11 Connection point of resistors 19 and 20 che20

25

the output of the first integrator 1; Q is the voltage at the inputs of the first and second integrators; e. —the voltage at the output of the selection unit 3 — 15 ki-storage; , is the voltage at the output of the second integrator 2; i-- is the voltage at the output of comparator 4; k - is the voltage at the output of the driver 5 pulses; k is the voltage at the output of the source 9 of the reference voltage; l is the voltage at the output of the integrator 10.

The frequency multiplier works as follows.

In the initial state, before switching on the supply voltages, the capacitors of all three integrators are discharged and the voltage at their outputs is zero. After switching on the supply voltage when a pulse arrives (Fig. 3a) on the input bus 8 of the control block 7, it generates a sequence of control pulses (Fig. 3b) that records the output voltage of the integrator 1 in block 3 of the storage capacitor and the subsequent discharge of the capacitor integrator 1 to level zero.

The voltage U (fig.Zg) at the output of the integrator 1 at the moment at

 of the pulse to the input bus 8 is determined by the magnitude of the voltage U ((fig.Zd) at the output of the integrator and the period T of the pulse

thirty

45

and.

° °. R.Ci

UoTi

(one)

50

55

where t is constant time first

integrator.

From (1), it follows that for a given value of U, the voltage U at the output of the first integrator, and therefore the voltage at the output of sampling-storage unit 3, is proportional to the pulse duration on the input bus 8. The output voltage of sampling-storage unit 3 is compared with voltage U2 at the output of the second integrator 2.

a cut in series connected and counter-connected Zener diodes 21 and 22 is connected to a common bus.

Figure 3 shows the timing diagrams of the device: L-- voltage on the input bus 8; - voltage at the first output of block 7

f control; o - voltage on the second

the output of the first integrator 1; Q is the voltage at the inputs of the first and second integrators; e. - voltage at the output of sampling-storage unit 3; , is the voltage at the output of the second integrator 2; i-- is the voltage at the output of comparator 4; k - is the voltage at the output of the driver 5 pulses; k is the voltage at the output of the source 9 of the reference voltage; l is the voltage at the output of the integrator 10.

The frequency multiplier works as follows.

In the initial state, before switching on the supply voltages, the capacitors of all three integrators are discharged and the voltage at their outputs is zero. After switching on the supply voltage when a pulse arrives (Fig. 3a) on the input bus 8 of the control block 7, it generates a sequence of control pulses (Fig. 3b) recording the output voltage of the integrator 1 in the block 3 of sampling and storage and the subsequent discharge of the capacitor integrator 1 to level zero.

The voltage U (Fig. 3g) at the output of the integrator 1 at the time of arrival of the pulse on the input bus 8 is determined by the voltage U ((Fig. 3d) at the output of the integrator and the pulse period T

and.

° °. R.Ci

UoTi

(one)

50

55

where t is constant time first

integrator.

From (1) it follows that for a given value of U, the voltage U at the output of the first integrator, and hence the voltage at the output of sampling-storage unit 3, is proportional to the period of the pulses on the input bus 8. The output voltage of sampling-storage unit 3 compared with the voltage U2 at the output of the second integrator 2.

The voltage U at the output of the second integrator is determined by the voltage and at its input and the period T of pulses generated at the output of the driver 5

and, and „

T, (2)

and.

I, S,

one-

g

where L is the time of the second

integrator.

The impulse at the output of the imager 5 is formed when the comparator 4 is activated, which occurs when the voltages at its inputs U U are equal, From (1) and (2) it follows

IG

-T,

The pulses on the output bus 6 are N times greater than the frequency of the pulses on the input bus 8 of the device. The multiplier factor N, as can be seen from (3), does not depend on the voltage at the inputs of the integrators 1 and 2 and is determined only by the ratio of their constant integration C t.

As the frequency of the pulses on the input bus 8 increases, the voltage Uj. at the output of the first integrator 1 at the time of arrival of the next pulse, the voltage at the output of the sampling-storage unit 3 is also reduced. As long as the voltage at the output of the sample-storage unit 3 is greater (in absolute value) than the voltage at the output

20 solutions at the input and output of elements at the level ensures high accuracy of their operation in terms of noise and interference,

Block 11 of the reference voltage and

those. the period T of the output pulses of the multiplier is proportional to the period T of the input pulses and the ratio of the constant time Cz. S respectively

second and first integrators. So OR i /, L - “, diodes 14 and 15 provide the maximum image, with i ,, L, - N the frequency is im- -. ..

 current voltage range Uo

at the input of integrators 1 and 2. In this case, the minimum level is determined by divider 13, which sets the voltage value at the output of the first integrator at the lowest frequency of pulses on the input bus. In addition, diode 18 and zener diodes 21 and 22 eliminate the influence of the pulsed power supply voltage 35 on the accuracy of the multiplier and increase the speed of the circuit with the third integrator, since its output voltage, regardless of sign, changes the value of voltage Ue 40 at the inputs of the integrators 1 and 2.

The proposed pulse frequency multiplier has a high speed, since the frequency of the output source 9 of the reference voltage, the pulse voltage, is determined only by the time at the output of the third integral interval (Xj) of the inter-interval 10 negative. Two preceding pulses. When the voltage at the output of block 3 at the signal input and does not depend on the sample storage, becomes less than the time constant of the third integrator determined by the source 9, 50 of the ra- tor, which provides the output voltage of the third integrator. The accuracy and range expansion begins to change and becomes positive, which increases the input voltage Up of integrators 1 and 2.55

In stationary mode, as the frequency of the input pulses increases, the output of the third integrator is set to the voltage at which

at working frequencies.

Claims (3)

1. A pulse frequency multiplier comprising the first and second integrators, a reference voltage source and a sample-storage unit.  , input voltage U, integrators 1 and 2 increase to such an extent that the minimum voltage is ensured g Uv at the output of the sampling-storage unit 3 at a level determined by the source 9 of the reference voltage. With a given accuracy which is determined by the minimum allowable 10 level Up and and, it allows in 100-1000 times extend the operating frequency range of the multiplier, since the units of the proposed device operate at sufficiently high levels of input and output signals, which reduces the influence of leakage currents, interference and interference, as well as temporal and temperature instability of other elements. Maintaining the operating voltages at the input and output of elements at a level ensures high accuracy of their work in terms of interference and interference, Block 11 of the reference voltage and OR i /, L - "The proposed pulse frequency multiplier has a high speed, since the frequency of the output pulses is determined only by the time interval (period Xj) between the two preceding pulses at the signal input and does not depend on the time constant of the third integrator, which provides increased accuracy and range expansion. at working frequencies. Invention Formula 1. A pulse frequency multiplier comprising the first and second integrators, a reference voltage source and a sample-storage unit. whose input is connected to the output of the first integrator, and the output to the first fy input of the comparator, the output of which is connected to the input of the pulse former, the output of which is connected to the output bus and the clock input of the second integrator, the input bus connected to the input of the control unit, the first output of which is connected with the clock input of the first integrator, and the second one with the control input of the sampling-storage unit, which is I with the fact that, in order to expand the working frequency range while maintaining accuracy, third integral a torus and a reference voltage unit, the input of which is connected to the output of the third integrator, and the output is connected to the inputs of the first and second integrators, the first input of the third integrator connected to the output of the sampling-storage unit, and the second to the output of the reference voltage source, the second input of the comparator is connected to the output of the second integrator. . 10 20 15 25 2, a multiplier according to claim 1, characterized in that the reference voltage block contains a source of reference voltage, the output of which is connected through a voltage divider to the anode of the first diode, the cathode of which is connected to the output of the reference voltage block and the cathode of the second diode, the anode of which connected to the input of the reference block. 3. The multiplier according to claim 1, characterized in that the reference voltage block contains a reference voltage source, the output of which is connected via a divider to the anode of a diode, the cathode of which is connected to the output of the reference voltage block and the second resistors with the input of the voltage reference unit, and the connection point of the first and second resistors are connected to the common bus through serially connected and counter-connected first and second zener diodes. I 1f  tl.M iОХЧГ  7Sig 20 city of Editor L.Pcholinsk Compiled by Sazonov Tehred I. Veres Order 3591/55 Circulation 901 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 Fig.Z Proofreader V. But ha