SU1275755A1 - Versions of pulse distributor - Google Patents

Abstract

The invention relates to a pulse technique. It can be used in devices and systems of automation and computing technology in measuring devices, as well as in microelectronics to create micro circuits - pulse distributors. W 7d Fig. 1. The purpose of the invention is to expand the functionality by implementing the device functions of the pulse distributor both to an even and an odd number of output tires. The distributor is built on QC triggers and pulse keys with control signal memorization. It contains 1.1-l.n triggers according to the number of bits, additional trigger 2, pulse keys 3 and 4 with control signal memorization, OR-NOT 5.1-5 elements. According to the number of bits, input line 6, output buses 7.17 .p. It can be used in integrated circuits and manufactured in the form of a microcircuit. It is possible to interconnect two or more pulse distribution patterns. 2 sec. f-ly, 5 ill.

Description

The invention relates to a pulse technique and can be used in devices and systems of automation and computer technology, in measuring devices, as well as in microelectronics to create pulse distributor microchips. The purpose of the invention is the extension of functionality due to the implementation by the device of the function of the impeller distributor both on an odd and an even number of output edges. Fig, 1 shows a diagram of the pulse distributor in the first embodiment; in fig. 2 - temporary g 1 of his work; in fig. 3 is a pulse key diagram with a control signal memorization; in fig. 4 - the scheme of the pulse distributor is presented, according to the second variant; in fig. 5 shows a circuit for connecting the pulse distributors of the second embodiment with one another. The pulse distributor contains triggers 1, -1 according to the number of bits, the additional trigger 2, the first 3 and second 4 impulse keys with the control signal memorization, elements ICH-NOT 5, - 5n according to the number of bits, input bus 6, output buses 7 -, 7 FIG. 2 shows: signal 8 on the input bus 6, signals 9-13, respectively, on the output buses 7, -7. Each pulse key 3 and 4 contains the first 14, second 15, third 16, and fourth 17 elements OR NOT, inverter 18, control input 19, input bus 20, first 21, and second 22 outputs. In the second embodiment, the pulse distributor (Fig. 4) also contains a second additional trigger 23 and an OR 24 element, a reset input 25, a control input 26, a reset output 27, and a control output 28. The first impulse switch 3 is designed with an extension to the control input, and each bit contains an OR-NOT 5 element, the output of which is the output bus 7 of the pulse distributor. The first and second outputs of the element OR NOT 5 of each bit. connected to the inverted output of the trigger 1 of this bit and directly to the output of the trigger 1 of the next bit, input S of the first trigger 11, the second inputs R of the trigger 1 of the 55 bits and the first input R of the additional trigger 2 are connected and connected to the output The second pulse key 4, the switching input of which is connected to the input ;, bus 6 of the pulse distributor, and the control input is connected to the output of the last bit and connected to the first control input of the first pulse key 3, the second control input of which is connected to the output the additional trigger 2, the input S and the first input R of which are connected respectively to the first and second outputs of the first pulse key 3. The pulse distributor operates as follows. The first signal 8 (Fig. 2) from the input bus 6 is switched to the first outputs of keys 3 and 4, and the pulse from the first output of the first key 3 switches the trigger 1 and the additional trigger 2 to the unit state. As a result, on the output bus 7, a cut of the signal 9 is formed and on the output bus 7 the front of the signal 10. In this case, the trigger 1, switches to the zero state. The second signal 8 from the input bus 6 is switched to the first unused output of the second key 4 and to the second output of the first key 3. As a result, the trigger 1 switches to the unit state, and the trigger 1 and the additional trigger 2 go to the zero state. On the output bus 7j, the front of the signal 11 is formed. Similarly to the third and fourth signals 8, signals 12 and 13 are switched from the input bus 6 to the output buses 7 and 7, respectively. Switching trigger 1 to one state results in a control signal at the V-control inputs of the first 3 and second 4 keys per unit. The next pulse received on the input bus 6 is switched to the second output of the keys 3 and 4 and sets the device to the initial state. Thus, the proposed distributor has more functionality due to the implementation of the distributor both on the even and on the odd number of input tires. 3 1. The pulse distributor, which contains triggers on the number of bits, the first and second pulse keys with the control signal memorization and the additional trigger with the extension on OR on the R input, and the bit triggers, except for the first bit, have input R is an extension of PfflH, and input of S is an extension of AND, the output of the trigger of each bit is connected to the first input S of the trigger of the next bit and the first input R of the previous bit, the seconds of the S inputs of even and odd digits, except the first one directly to the first and second outputs of the first pulse key, the switching input C of which is the input bus of the pulse distributors, characterized in that, in order to expand its functionality, in it the first pulse key is made with an extension on the control input V, and each contains the element SHSHN, the output of which is the corresponding output bus of the pulse distributor, and the first and second inputs of the element YLI-NOT of each bit are connected to the inverse output of the trigger of this bit and the direct output t the next bit trigger, the S input of the first bit trigger, the second R inputs of the remaining bits and the first input of the additional trigger are connected and connected to the output of the second pulse key, the switching input of which is connected to the jK input of the pulse distributor, and the control input V The second pulse key is connected to the output of the last bit and connected to the first control input V of the first pulse key, the second INPUT of control V of which is connected to the output of the auxiliary trigger, input S and the first input R of which o are connected respectively to the first and second outputs of the first pulse key. 2. A pulse distributor containing triggers on the number of bits of the first and second pulse keys with signal storage. An additional trigger with an extension of the EOI on the input R, and the triggers, besides the first bit, have 554 on the input of the R extension on OR, and on input S - an extension on AND, the output of the trigger of each bit is connected to the first input S of the trigger of the next bit and the first input R of the trigger i of the previous bit, the second inputs S of the even and odd bit triggers, except the first, are connected respectively to the first and the second outputs of the first pulse key, the switching input of which is an input bus of the pulse distributor, different from the fact that, in order to expand its functionality, it contains a second additional trigger and an OR element, the first pulse key is output on the control input V with an OR extension, each bit contains an OR-NOT element whose output: is a corresponding output bus, and the first and second inputs of the ORIT element of each bit are connected to the inverse output of the trigger of this bit and direct trigger output of the next bit, input S of the first trigger, the second inputs R of the remaining bits and the first input R of the first additional trigger are connected and connected to the output of the OR element, the first input of which is connected to the output of the second pulse key, switching input which is connected to the input bus of the pulse distributor, the control input of the second pulse key is connected to the first control input of the first pulse key and connected to the control input of the pulse distributor, the reset input to The second control input of the first pulse key is connected to the output of the first additional trigger, the input S and the first input R of which are connected respectively to the first and second outputs of the first pulse key, and the outputs 1 and S of the second additional trigger are connected to the output of the last bit trigger and the output of the element OR, respectively, the second inputs S of the triggers of even and odd times, except the trigger of the first discharge, are connected respectively to the first and second outputs of the first mulsnogo key, the first input R Triger latter is connected to the discharge rugomu, compared to the second input S of the flip-flop, the output i of the first switch pulse and inverted output of the second further flip-flop and

the output of the OR element is the first and second additional outputs of the pulse distributor.

Vshod1

dsho & 2

vshod 2 breathing

8b / bt / xo l kodo

Claims (2)

Claim 1. A pulse distributor containing triggers by the number of bits, the first and second pulse keys with 5 memorizing the control signal and an additional trigger with OR expansion at the input of R, moreover, the trigger of the digits, except for the first bit, have OR expansion at the input R , ¹⁰ and the input S is the expansion in I, the trigger output of each discharge is connected to the first input S of the trigger of the next discharge and the first input R of the trigger of the previous discharge, the second '5 inputs S of the triggers of even and odd digits, except the first, are connected respectively to the first the second and second outputs of the first pulse switch, the switching input of which is the 20 input bus of the pulse distributors, characterized in that, in order to expand its functionality, the first pulse switch in it is made with 25 expansion at the control input V, and 'each bit contains ORINE element, the output of which is the corresponding output bus of the pulse distributor, and the first and second For the inputs of the YPI-NOT element of each discharge are connected to the inverse output of the trigger of this discharge and the direct output of the trigger with eduyuschego discharge input S Perry discharge trigger secondary rye inputs R ₃₅ triggers the remaining bits and the first additional trigger input coupled and connected to the output of the second pulse switch, the switching input C is connected _{to 40} (shift to the input impulrov distributor, and a second control input V the pulse key is connected to the output of the last bit and connected to the first control input V of the first pulse key 45, the second · control input V of which is connected to the output of the additional trigger, input S and the first input R of which keys respectively to first and second outputs of the first pulse 50 key. 2. A pulse distributor containing triggers by the number of digits, the first and second pulse keys with the signal memorization. Control and 55 additional trigger with expansion by OR at the input R, and the triggers of the digits, except the first bit, have an OR extension by input R , and at the input S - expansion in And, the trigger output of each discharge is connected to the first input S of the trigger of the next discharge and the first input R of the trigger of the previous discharge, the second inputs S of the triggers of even and odd digits, except the first, are connected respectively to the first m and the second outputs of the first pulse switch, the switching input of which is the input bus of the pulse distributor, characterized in that, in order to expand its functionality, it contains a second additional trigger and an OR element, the first pulse switch is made at the control input V with extension by OR, each bit contains an OR-HE element, the output of which is the corresponding output bus, and the first and second inputs of the OR element are NOT connected to the inverse output of the trigger of this discharge and directly the output of the trigger of the next category, the input S of the trigger of the first category, the second inputs R of the triggers of the remaining bits and the first input R of the first additional trigger are connected and connected to the output of the OR element, the first input of which is connected to the output of the second pulse switch, the switching input of which is connected to the input bus pulse distributor, the control input of the second pulse switch is connected to the first control input of the first pulse switch and connected to the control input of the pulse distributor, the reset input of which is connected to the second input of the OR element, the second control input of the first pulse switch is connected to the output of the first additional trigger, the input S and the first input R of which are connected respectively to the first and second outputs of the first pulse switch, and the outputs I and S of the second additional trigger are connected to the output of the trigger the last bit and the output of the OR element, respectively, the second inputs S of the triggers of even and odd bits, except for the trigger of the first discharge, are connected respectively to the first and second outputs of the first pulse of the key, the first input R of the trigger of the last digit is connected to another, compared with the second input s house S of this trigger, the output of the first pulse of the key, and the inverse output of the second additional trigger and the output of the OR element are the first and second additional outputs of the pulse distributor. β code 1 n n P P n n n n P Would move δ MM "| gp . r-i ¹⁰ Exit! I -------------- 1 GT Output g G 1 J “1 Exit3 G η G “1 ^ Vkodch G “ 1 r ~ Figure 2 b Fig 5