SU1501036A1 - Uniform-structure cell - Google Patents

Abstract

The invention relates to automation and computing and is intended to build homogeneous plane structures that implement arbitrary logical functions. The purpose of the invention is to reduce hardware costs in the construction of homogeneous structures. The cell contains information inputs 1 and 2, configuration inputs 3 and 4, majority element 5, elements AND 6 and 7, element BAN 8, elements OR 9 and 10, outputs 11 and 12. When setting the signals belonging to the set {0,1 }, The cell implements four kinds of functions. 1 tab., 3 Il.

Description

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The invention relates to automation and computing and can be used to build homogeneous planar structures that implement arbitrary normal formulas (including any brackets) of h letters, specified in the basis of AND, OR, NOT under the condition of equal availability of direct and inverse outputs of information sources.

The purpose of the invention is to reduce the redundancy of a homogeneous structure by changing the functionality of the cell.

FIG. 1 shows the functional scheme of the cell; in fig. 2 - switching and functional circuits implemented by the cell by setting it up; in fig. 3 is an example of the implementation of a formula with a tree-like scheme embedded in a homogeneous structure.

The cell contains the first 1 and second 2 information inputs, the first 3 and second 4 configuration inputs, the three-input major element 5, the first 6 and second 7 elements AND, the BAN element 8, the first 9 and second 10 elements OR, the first 11 and second 12 cell exits.

The cell structure is described by the following formula system.

f, a ,, Z, (a, v a) Z, 1 g

The cell works as follows.

Non-external inputs 1-4 cells are provided with logical variables or their inversions, as well as constants O and 1, depending on the type of implemented function required in accordance with the table.

In the general case, to implement an arbitrary function given by a normal formula of h letters, in the basis of AND, OR, NOT with. equal availability of direct and inverse outputs of information sources, a tree diagram of two-input AND and OR input elements is built, which is embedded in a rectangular planar homogeneous cell structure, with one cascade of the circuit in each row of the structure. By cascades is a line.

on a homogeneous structure of the maximum number of elements AND and OR, included in the tree structure, each element being included in only one cascade.

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The cells of the structure corresponding to the AND (OR) elements of the tree diagram are configured to implement the scheme of FIG. 25 or the diagrams of FIG. 2b. The remaining cells of the structure are tuned to implement the circuit of FIG. 2ct.

Input variables are fed to a homogeneous structure as follows.

The variables corresponding to the first input of the initial element of the i-ro cascade of the tree are fed to the input of the i-th row (i 1,2, ..., h / 2) of a homogeneous structure. The remaining variables are fed to the inputs of the structure columns, in which cells are located corresponding to the elements of the tree, the second inputs of which are connected to the inputs of the variables.

The output variable is removed from the output of the first line of the structure.

FIG. 3 shows a homogeneous structure, configured to implement the formula:

Y (X, V X) (XU X) V (XB) (X Xg) i

(Xgv x,) (x ,, vx, pv (x, vx,) (x, 5vV

The switching and functional capabilities of the proposed cell allow the input of each column of the structure to be used to supply the input variable. Therefore, the number of cells in a homogeneous structure and the required number of configuration inputs are determined by the ratios

L (h - K) K, S 2 (h - K) K,

where K is the number of cascades in the tree.

Claims (1)

Invention Formula The homogeneous structure cell containing the BANE element, the AND element and the majority element, the first information input of the cell is connected to the first input of the majority element, the second information, and the second input of the cell is connected to the first input of the first element And, that, in order to reduce hardware costs, it contains the second element AND, the first and second elements OR, and the first setup input of the cell is connected to the second input of the majority element, the first information input of the cell is connected to the first input second The I element, the second input of which is connected to the second tuning input of the cell, the second input of the first element AND, and the inverse input of the BAN element, the direct input of which is connected to the output of the primary element, the third input of which is connected the first output of which is connected to the output of the first element OR, the first input of which is connected to the output of the second element AND, the second input of the first element OR I f o Qfi of about s / g connected to the output of the element BAN and the first input of the second e. OR, the second input of which is connected to the output of the first element AND, and the output of the second element IS1 is connected to the second output of the cell. ET :: ii :: i about 1 about 1 a, va a, Va, Note Fig.25 2 a Fig.2b 2 a  Of