SU1272293A1 - Former of directional pattern - Google Patents

Abstract

The invention relates to a technique for determining the direction from which radio or acoustic oscillations come. The purpose of the invention is to expand the frequency range of operation of the driver. The shaper contains a p-element antenna 1, rc 2 clock pulses, a n-input adder 3, a frequency divider 7 and n signal processing units 4, each consisting of ADC 5, two delay blocks (BZ) 6 and 8, and a memory block TI (BP) 9. The appearance of a pulse at the output of the BZ 8 determines the moments of reference, i.e. moments of obtaining sample values of the analog signal, which are converted by each A / D converter 5 into a diffracted form. This digital code is transmitted to BP 9, where it is stored until the next reference time. Digital codes from BP 9 are transmitted to BR 6, the period where the frequency of the divider 7 is delayed by several odes, after which (L are summed up and transmitted to the output of the driver. The goal is achieved by introducing the divider 7, BR 8 and BP 9. 1 or ts5 Is3 CO GO

Description

The invention relates to a technique for determining the direction from which radio or acoustic oscillations come.

The purpose of the invention is the expansion of the frequency range of the device.

The drawing depicted a structural electrical driver beam pattern.

The imaging unit contains an l-element antenna 1, a generator of 2 clock pulses, a p-input adder 3, the output of which is the output of the device TBIE fi of blocks A.1-4. Signal processing units each of them consist of an analog-to-digital converter (ADC) 5 The information input of which is connected to the output of the corresponding antenna element, and the first delay delay block 6, the output of which is connected to the corresponding input of the adder, as well as the frequency divider 7, the input of which is connected to the generator output 2 clock pulses, and in each of the blocks, n processing signal ki — a second delay unit 8 and a memory unit 9, the output of the second delay unit 8 is connected to clock inputs — ADC 5 and memory block 9, whose information input is connected to the output of ADC 5, and the output information input of the first block 6 is delayed the input of the second delay unit 8 and the clock input of the first delay unit 6 are connected to the output of the frequency divider 7, and the clock input of the second delay unit 8 is connected to the generator output 2 clock pulses „

The shaper pattern works as follows.

The signals from the outputs of the elements of the antenna 1 are fed to the information inputs of the ADC 5 corresponding blocks A.14, 1 signal processing. The moments of reference, i.e., the sampling values of the analog signal that are pre-formed by each ADC 5 in a digital form are determined by the appearance of a pulse at the output of the second delay unit 8. The digital code from the output of the ADC 5 is transmitted to memory block 9 where it is stored until the next reference point. Under the action of the frequency pulse f, coming from the output of the frequency divider 7, simultaneously the clock inputs of all the delay blocks 6. Digital codes from memory blocks 9 are transmitted to the corresponding blocks 6

delays, where the frequencies fg are delayed for several periods, after which they are fed to the inputs of the adder 3, after summation are transmitted to the output of the device.

The delay time of the signal in the circuit of each processing unit 4.1-4.h has two components. The first is equal to the period TD of the frequency d; it is taken to convert the level of the analog signal into digital form. The second component is equal to the sum of the delay time in the delay block 6 and the delay time in the memory block 9, which is controlled by a signal from the output of the second delay block B. The delay time of the signal in memory block 9 is the difference between the storage time of the code in memory block 9, which is equal to Tg, and the delay time in the second delay block 8. If the first and second delay blocks have the number of delay elements equal to k and Ij respectively, then the delay time is defined as the product of the number of delay elements and the period of the clock

"Frequencies equal to kT and - for the first

and the second delay units, respectively, where n is the division factor of the frequency divider 7.

Thus, the total signal delay time in a separate signal processing unit is equal to

  T „+ kT + (T„ -).

By changing k, you can change the delay time in increments of T, and by changing I, you can change the delay time with more

T

small step -. Consequently, by changing k and 1, it is possible to form a radiation pattern with a main maximum in the required direction, and the step of changing this direction is controlled by a period of 2 tacho pulses of T pulses equal to Tj. At that

At the same time, the clock frequency of operation of the main blocks of the device: ADC 5, memory blocks 9, first delay blocks 6 is m times less than the frequency of the generator 2 clock pulses. This allows either to reduce the speed requirements of these units, or to expand the frequency range of the device.

312722934

Claims (1)

The invention of the frequency, the input of which is connected to The driver of the directional diagram, and in each processing unit of the sigkost containing the h Element antenna, there is a second delay unit and Well, a clock generator, a input adder, the output of which is a device output, n signal processing units, each of which consists of an analog-digital converter, whose information input is connected to the output of the corresponding antenna element and the first delay unit, the output of which is connected a corresponding adder input, characterized in that, in order to expand the frequency range of the device, a divider is introduced the output of the generator. tactic pulses, the output of the second delay unit is connected to the clocks of the analog-digital converter and the memory block, whose information input is connected to the output of the analog-digital converter, and the output to the information input of the first delay block, the information of the second delay block and the clock input the first delay block connected to the output frequency divider and clock input second delay unit connected to the output of the clock generator.