SU1379941A1 - Analog-digital converter with measurement range autoselection - Google Patents

Abstract

The invention relates to digital information measuring technology and can be used in information measuring and control systems. The purpose of the invention is to improve the conversion accuracy by reducing the reduced error. The device comprises an analog memory unit 1, a scale unit 2, an analog-digital converter 3, an arithmetic logic unit 9, a synchronization unit 8, a scale register 10, a scale selection unit 4. The device has changed the functional connections and the possibility of adaptive adjustment of the gain factor has been made to bring the input signal to a value close to the upper conversion limit of the A / D converter. 2 hp f-ly. 1 il. (ABOUT

Description

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The invention relates to a digital information-measuring technique and can be used for converting analog signals into a digital code and information measurement systems and control systems, as well as for comp. digital computer calculators - N.YH f-iaruHH with analog channels, 1-1011 (large dynamic range of signal zones.

The purpose of the invention is to improve the accuracy of converting an analog signal to a 1-digit code by reducing the reduced error of the analog-to-digital conversion.

The drawing shows a block diagram of an analog-to-digital conversion device with an automatic Ryboro; -1 measurement limit .20

The device contains an analog zapo inan block 1, a scale unit 2, an analog-digital converter 3, a scale selection unit 4 including a permanent storage device 5, 5 digital divider 6, as well as a register 7, a synchronization unit 8, an arithmetic logic unit 9, register 10 scale, element YAPI 11, bus 12 Start, timer 13.30

The essence of the invention is as follows.

The given error makes a noticeable share in the error of the analog-digital conversion devices and 5 is determined by the time frame.

r f x

where Xp is the price of the least significant bit of the analog-digital converter;

X is the value of the converted analog signal.

It follows from the expression that it takes the smallest value when X accepts the greatest. Thus, in order to reduce the value of S pp, it is necessary to perform the conversion of the analogue-Boi o signal in the range close to the upper limit of the conversion. 50

For this, in the device, an analog signal is supplied to the first input of the analog storage unit 1 from the input bus. Upon a command of Starting from the second output of the synchronization unit 8, an uplip signal is fed to the second input of the analog storage unit 1 and the third input of the scale register 10. At the same time with

the first output of the synchronization unit 8 is supplied with a control signal to the first input of the analog-digital converter 3, while in the analog memory unit 1 the value of the analog signal X is fixed. From the output of the scale register 10 to the second input of the scale unit 2 the code sets the scale factor transform. Analog-to-digital converter 3 converts the signal received from the output of block 1 of analog storage through block 3 of a scale on its second input (the value of the signal at the input of analog-to-digital converter 3 is Kp. X) into digital code N ,. This code is fed to the second inputs of the scale selector 4 and the first input of the arithmetic logic unit 9.

A control signal is supplied to the first input of the scale selection unit 4 from the fourth clock of the synchronization unit 8. In this case, in block 4 of the scale selection, the value of the model code N ,, g (- the code corresponding to X,) is divided by the value of the code Ny. The division result is rounded to the nearest smaller code value corresponding to the nearest smaller conversion rate of block 2 of scale K. The code corresponding to the rounded result of division / NX is supplied from the output of scale selector 4 to the second input of scale register 10.

Then, from the third output of the synchronization unit 8, a control signal is supplied to the third input of the arithmetic logic unit 9 and the first input of the scale register 10. Simultaneously, from the first output of the synchronization unit 8, a control signal is supplied to the first input of the analog-digital converter 3. At the same time, from the output of the scale register 10 to the second inputs of the scale unit 3 and the arithmetic logic unit 9, a code corresponding to a certain division result is supplied sets the scale conversion factor in block 2 scale, g / N. Analog-to-digital converter 3 converts the signal from the output of the block

1 analog storage through block

2scale to its second input (the value of the signal at the input of the digital-to-digital converter 3 is XK), to the digital code N. In the arithmetic logic unit 9, the scale is taken into account by dividing the code N value by the code value corresponding to the rounded dividing result // N,

Thus, from the output of the arithmetic logic unit 9, the code is removed

N ylln ny

The device works as follows.

Upon a command of the start of the second synchronization device, a signal is generated that the value of the converted signal X is fixed in block 1 of the analog storage, the scale register 10 is set to one of the stable states with the same signal, and from its output the code is fed to the second the input of the scale unit 2, which sets the scale in it, the transmission coefficient K 1. At the same time, the same signal through the element OR 11 is fed to the first input of the analog-digital converter 3, by which it converts the incoming signal to its second The input signal X is in the digital code NK, which is entered in register 7.

Then, at the first output of the timer 13, a signal is generated, from which the output of the register 7 to the second input of the digital divider 6 is given the code N, and to its first input from the output of the permanent storage device 5 - the code. In the digital divider b, the codes Nng / Nx are divided and the result of the division to the nearest smaller code value corresponding to the nearest smaller Q is rounded, and the code corresponding to the rounded result of division is fed from its output to the scale register 10.

Then, at the third output of the timer 13, a signal is formed, which, from the input of the scale register 10, supplies the code to the second input of block 9 and the second input of block 2, which sets Kf in them; corresponding to the rounded result of division, / / N. The same signal through the element OR 11 is fed to the first input of an analog-to-digital converter 3, which converts the signal X-Kn ;, coming to its second input from the output of block 2

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the scale, into the digital code N. The code N, goes to the first input of block 9, in which the scale is taken into account by dividing the code N, by the code corresponding to Kq. .

Thus, at its output, an adjustment result is obtained for the transformation

N K,

 formula of invention

Claims (2)

1. Analog-1Shfra device with automatic selection of the measurement limit, containing an analog storage unit, a scale unit, a scale selection unit, an analog-to-digital converter, the outputs of which are connected to the corresponding first inputs of the arithmetic logic unit, the first input of the analog-digital converter is connected to. the first output of the synchronization unit, the second output of which is connected to the first input of the analog storage unit, the input is the Start bus, The third output is connected to the first input of the scale register, the second inputs of which are connected to the corresponding outputs of the scale selection unit, and the outputs are connected to the corresponding second inputs of the arithmetic-logging block whose outputs are output bus, characterized in that conversion accuracy by reducing the reduced error, the second input of the analog storage unit is an input bus, the output is connected to the first input of the scale unit, the output of which is connected to the second input analog -digital converter, and the second inputs - with the corresponding outputs of the scale register, the third input of which is connected to the second output of the synchronization unit, the fourth output of which is connected to the first input of the scale selection unit, the second inputs of which are connected to the corresponding outputs of the analog-digital converter, the third output of the block synchronization is connected with the third input of the arithmetic-glop-block. 2. The device according to claim 1, about tl and - so that the block selection scale is made on the register. 5 13799416 fixed storage device3. The device according to claim 2, of which is a digital divider, the outputs of which, in that the sync block is the output of the block, and the first release is performed on the element OR the inputs are connected to the corresponding timer, the input of which is outlets of the permanently memorized path of the block, the first exit is the device, the input of which is the fourth output of the block, the second output with the first input of the register and is connected to the first input of the element the first input of the block, the outputs of the register, and is the second output of the block, connected to the corresponding second and third output connected to the second input the inputs of the digital divider, and the second OR elements and the third output are the second inputs by the block block, and the output of the OR element is the first output of the block.