JPS6031313A - Output stabilizing circuit of a/d converter - Google Patents

Abstract

PURPOSE:To make a digital output stable against quantized noise by providing an A/D converter, a latch circuit and a control means for comparator and latch circuit to an output stabilizing circuit and comparing an output value of the A/D converter held in the latch circuit and an output value after the A/D converter. CONSTITUTION:Continuous number of time control sections 43, 44 discriminate that a new converting output S6 is larger or smaller than a stored converting output S5 continuously by a preset nember of times based on an output of shift registers 41, 42. When the output is larger or smaller continuously for a prescribed number of times, the control sections 43, 44 give a control signal to a latch pulse generating section 45. As a result, a latch pulse is given from a latch pulse generating section 45 to a latch circuit 20 based on an AND output between a control signal and a latch pulse synchronizing clock S4, and a new converting output inputted to the latch circuit 20 is stored, then the digital output is changed.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application This invention relates to an output stabilization circuit for an A/D converter that stabilizes fluctuations in the output value of the A/D converter.

(B) Prior Art Generally, since A/D converters are extremely sensitive to fluctuations in input values, quantization noise is likely to be superimposed on their output.

This has the disadvantage that the operation of devices connected to it becomes unstable.

In order to eliminate this drawback, for example, the lower two bits of the 8-bit conversion data are ignored.
A method has been proposed to reduce the sensitivity of the D converter. However, even with this type of method, the output cannot be stabilized if, for example, the output data fluctuates between the lower 2 and 3rd bits.

(C) Objective The object of the present invention is to provide an output stabilization circuit for an A/D converter that can stabilize a digital output against quantization noise.

(d) Configuration The output stabilizing circuit of the A/D converter according to the present invention has an A/D converter output stabilizing circuit according to the present invention.
A D converter, a latch circuit, a comparator, and a latch circuit control means are provided, and the output value of the A/D converter held in the launch circuit is compared with the output value after the A/D converter. , when the output value after the A/D converter is larger or smaller than the held output value of the A/D converter for a predetermined number of consecutive times, the latch circuit control means sets A for the predetermined number of times. The present invention is characterized in that the output value of the /D converter is held in a launch circuit, and the held output value is taken out as a digital output.

(E) Embodiment FIG. 1 is a block diagram schematically showing the configuration of an embodiment of an output stabilizing circuit for an A/D converter according to the present invention.

In the figure, 10 is an A/D converter, 2o is a latch circuit that holds the output of the A/D converter 10, and 30 is the output value of the A/D converter 10 held in the latch circuit 20 and the A/D converter. A comparator 40 for comparing the output value after the converter 10 is given the comparison output of the comparator 3o, and the output value after the A/D converter 10 is higher than the held output value of the A/D converter 1o. If the output value of A/D converter is continuously large or small for a predetermined number of times, the launch circuit control means 50 causes the launch circuit 20 to hold the output value of the A/D converter for the predetermined number of times. /D converter 10 and launch circuit control means 4
This is a clock control section that controls the operation of G.

The circuit control unit 40 has shifters 1 to 1 which receive a large signal or a small signal from the comparator 30, respectively.
Continuous number of times to determine whether the output value after the A/D converter 10 is larger or smaller than the held output value for a predetermined number of consecutive times based on the outputs of the resistors 41 and 42 and each shift register 41.42 It includes control sections 43 and 44, and a launch pulse generation section 45 that applies latch pulses to the latch circuit 20 based on signals from the consecutive number control sections 43 and 44.

Next, the operation of the embodiment having the above-described configuration will be explained.

The clock control unit 50 controls A based on the system clock.
A conversion start pulse S1 of a predetermined period is given to the /D converter 10. The A/D converter 10 converts the analog input into a digital value at each cycle and provides a conversion end pulse S2 to the clock controller 50. The clock control unit 50 is
The shift clock S3 is sent to the shift registers 41 and 42 with a slight time delay from the conversion end pulse S2, and further,
The latch pulse generator 4 generates the latch pulse synchronization clock S4 with a slight time delay than the shift clock S3.
5 each.

On the other hand, the conversion output S5 of the A/D converter 10 held in the latch circuit 20 is given as one input to the comparator 30 and taken out as a digital output. The comparator 30 compares the conversion output S6 after the A/D converter 10 and the conversion output S5.
The comparison output S7 is applied to the shift register 41, and the concomitant output S8 of the comparison output S7 is applied to the shift register 42.

Based on the outputs of the shift registers 41 and 42, the consecutive number control units 43 and 44 determine whether the new conversion output S6 is continuously larger than the held conversion output S5 by a preset number of times or Determine whether it is small. If the value is continuously large or small a predetermined number of times, the control sections 43 and 44 give a control signal to the latch pulse generation section 45.

As a result, the control signal and the launch pulse synchronization clock S
Based on the AND output of 4, a latch pulse is applied from the launch pulse generator 45 to the latch circuit 20, and the new conversion output input to the latch circuit 20 is held, thereby changing the digital output.

The above operation will be explained in more detail by taking a 6-bit conversion output as an example.

FIG. 2 is an explanatory diagram showing changes in the conversion output of the A/D converter and corresponding changes in the output and digital output of the shift register.

For example, suppose that the conversion output of the A/D converter 10 changes in the order of ■ to [phase] as shown in the figure (al).The conversion output ■ is held in the latch circuit 20.
As a result of comparing the magnitudes of the and subsequent conversion outputs, the comparison outputs of the convolutions as shown in (B) and (C1) of FIG.

Here, for example, if the consecutive number of times is set to '3J' in advance in the consecutive number control section 43, 44, the conversion outputs ■ to ■ are larger than the held conversion output ■ three times in a row, so the third time is The conversion output ■ is newly held. the result,
As shown in (d) of the same figure, the digital output is
It changes from 00100 J to '101000 J.

Thereafter, the conversion output ■ and the next conversion output are compared in the same way. Therefore, since the conversion output [phase] becomes smaller than the conversion output ■ three times in succession, the conversion output 0 is maintained,
A new digital value "100111 J" is output.

Figure (e) shows such a change in the conversion output ■~[phase] (
(indicated by a broken line) and changes in the digital output (indicated by a solid line). From the same figure, compared to the change in conversion output,
It can be seen that the digital output is very stable.

(f) Effect The output stabilization circuit of the A/D converter according to the present invention compares the held conversion output and the next conversion output, and determines whether the next conversion output is higher than the held conversion output a predetermined number of times consecutively. Since the conversion output of the predetermined number of times becomes a new digital output only when the value becomes large or small, the digital output is stable against the quantization noise of the A/D converter, and
By appropriately setting the numerical value of the consecutive number of times, it is possible to follow the true output change of the A/D converter without any practical problem.

[Brief explanation of the drawing]

FIG. 1 is a block diagram schematically showing the configuration of an embodiment of an output stabilizing circuit for an A/D converter according to the present invention, and FIG.
FIG. 3 is an explanatory diagram showing changes in the conversion output of the /D converter and corresponding changes in the output and digital output of the shift register. 10... A/D converter, 20... Launch circuit, 30
. . . Comparator, 40 . . . Launch circuit control means, 41.
42... Shift register, 43.44... Continuous number control section, 45... Launch pulse generation section, 50... Clock control section. Patent applicant Shimadzu Corporation Representative Patent attorney Takaharu Ohnishi

Claims (1)

[Claims] (1) An A/D converter, a launch circuit, a comparator, and a launch circuit control means are provided, and the output value of the A/D converter held in the launch circuit and the output value after the A/D converter are Compared and held, the A/D converter output value is
When the output value after the converter is continuously large or small for a predetermined number of times, the launch circuit control means controls the A for the predetermined number of times.
1. An output stabilizing circuit for an A/D converter, characterized in that the output value of the A/D converter is held in a launch circuit, and the held output value is taken out as a digital output.