SU1267420A1 - Device for checking electronic units - Google Patents

Abstract

The invention relates to computing and can be used to control electronic analog (when using a DAC and ADC) and digital objects. The purpose of the invention is to expand the functionality of the device due to the time constraints on the removal of the result of the control. Device E) The 1st control of electronic components contains a memory block 1, a comparison block, a timer 4, a group of 5 elements AND, a block of 6 indices, element 7, an element OR 8, a counter 9, a decoder 10, input II of the initial start, monitored block 12; From block 1 of memory, the lower and upper limits of the tolerance field and test actions are received from the comparison blocks 2.3 and the controlled block. The result of the control is gated with a pulse from the timer output and is fed to the § 6 block of the display. Functional dissipation is achieved by (L inserting a timer, second comparison block, AND element, OR element, decoder and counter into this device. 1 Il.

Description

The invention relates to computing and can be used to control electronic analog when using {A11 and ADC and digital blocks.

The aim of the invention is to expand the field of application of the device.

The drawing shows the proposed device.

The device for monitoring electronic components contains a memory block I, comparison blocks 2 and 3, a timer. 4, the group of 5 elements AND, the display unit 6, the element AND 7, the element OR 8, the counter 9, the decoder 10, the input 1 of the initial start-up, the monitored block 12,

The device works in the following way.

In the initial position, the counter 9 is reset. The initial start signal coming from input 11, the counter 9 changes its state, fixes the unit, the content code of the counter 9 goes to the address inputs of the memory block, and to the input of the decoder 10, the latter determines the number of test patterns required for the control unit 12.

From the first memory block 1, the code combination of the lower margin of the tolerance field of the block 12 enters the first input of the comparison block 2. From the second output of the memory block 1, the test code combination enters the input of the block 12, From the third output of the memory block 1 to Timer 4 input receives a time delay code not lower than the allowable response time of the block 12; From the fourth output of block I, the first input of the comparison block 3 receives the code combination of the upper limit of the tolerance field of the reactions of block 12; blunt the second inputs of the blocks 2 and 3 are comparative.

According to the result of the comparison, blocks 2 and 3 of the comparison provide one of three signals at their outputs. Less, Equal, More, which corresponds to block 2 Below the tolerance floor, At the lower boundary, tolerance floor and Higher lower tolerance, and for block 3 Below the upper tolerance limit At the upper border, tolerance, Higher tolerance, respectively.

The result is the analog; from the output of the 2 and 3 units of comparison, it goes to the first inputs of elements AND of group 5, the second inputs of which are delayed

in the time specified by the code from the third output of memory block 1, timer 4 generates a short pulse, according to which the analysis result is fed to the display unit 6 and fixed

Claims (1)

there. If the response of block 12 is in the tolerance field, then at the output of element 7, a trigger pulse is generated, which is fed to the counting input of counter 9, the contents of the latter increase by one, the process repeats. Upon reaching a predetermined number of test actions, the Deshira, the grator 10 generates a signal to the input of the initial installation of the counter 9, the latter is zeroed, the device is in the initial state, the claims A device for controlling electronic units, comprising a first comparison unit, a memory unit, an indication unit and a group of elements I, the first output of the memory unit being connected to the first information input of the first comparison unit, characterized in that, in order to expand the field of application of the device, it has a second comparison block, a counter, a decryptor, a timer, an OR element and an AND element, with the second, third and fourth outputs of the memory block connected to the output of the device for connecting to the input of the monitored block, with the timer input and with the first information input of the second comparison unit, respectively, the second information inputs of the first and second comparison blocks are combined and connected to the input of the device for connecting to the output of the monitored block, outputs Less, Equal / More than the first and second comparison blocks are connected to the first inputs of the first, the second, third, fourth, fifth and sixth elements of the AND group, respectively, the second elements of the AND group are combined and connected to the output of the timer, the outputs of the first, second, fifth and sixth elements of the And group s are connected to respective inputs of the indication unit, the outputs of the third and fourth members and the group are respectively connected to the first and 3 12674204 by the second inputs of the element And and from the corresponding OR connected to the counting input by the corresponding inputs of the display unit, the counter, the input of the initial installation, the output of the element And connected to the first which is connected to the output of the descrambler of the element OR, the second input, the input of which is connected to the input initial j is the address input of the memory unit and the device is started up; the output is key to the output of the counter.