SU1259469A1 - Frequency multiplier - Google Patents

Abstract

This invention relates to a measurement technique. The inventive feed is an increase in device speed. The device contains an adder 4, two two-branch voltage dividers 5 and 6, two blocks 7 and 8 amplitude comparators. Trigger 1 and two formers 2 and 3 of triangular voltage were newly introduced. Rapid tuning with a frequency hopping is carried out for one period due to zeroing of the formers 2 and 3 by the input pulses during the decay of the generated triangular voltage. 2 Il. i (L SD D 4 Od F

Description

The invention relates to a measurement technique and can be used in low frequency conversion devices.

The purpose of the invention is to increase the speed of the device.

Figure 1 shows a structural electrical circuit; in fig. 2a, 5b, b, g, d, e timing diagrams for the operation of the frequency multiplier.

The frequency multiplier contains a trigger 1, the first driver 2 triangular voltage, the second driver 3 triangular voltage adder. 4, the first multi-voltage divider 5, the second multi-tap voltage divider 6, the first block 7 of amplitude comparators, the second block 8 of amplitude comparators.

The multiplier works as follows. . .

The periodic impulse sequence 1-) Owls (Fig. 2a) is fed to the county trigger input 1. Symmetric pulse sequence (Fig. 25) from the direct output of trigger 1 arrives to the input of the first forcing device 2, and from the inverse (Fig. 2B) - to - the input of the second driver 3. The triangular voltages from the outputs of the first and second drivers 2 and 3 are fed to the first inputs of the second and the first blocks 8 and 7, respectively, to the second inputs of which are fed, divided by the first and second multi-divider 5 and 6, the voltage in the opposite phase with and at the first inputs of the first and second blocks 7 and 8 (2 2.9).

The output pulses from the first and second blocks 7 and 8 are combined with the frequency pulses of the frequency multiplier in the adder 4 and a sequence of pulses is formed at the output of the adder 4 (Fig. 2e). The multiply frequency multiplier is determined by

the number of levels of comparison (Fig. 2 Q, g,) and is limited only by the parameters of the amplitude comparators of the first and second blocks 7 and 8.

A fast tuning of the frequency multiplier with an abrupt change in the input frequency is performed during one period by zeroing the first and second drivers 2 and 3 with the input pulses during the decay of the triangular voltage being formed (Fig. 2 tons).

Claims (1)

Invention Formula A frequency multiplier containing serially connected first multi-tap voltage divider, first block of amplitude comparators and adder, serially connected second multi-tap voltage divider and second block of amplitude comparators, the outputs of which are connected to the corresponding inputs of the adder, characterized by the fact that in order to increase speed, He introduced the first and second triangular voltage shapers and a trigger, while the direct output of the trigger is connected to the input of the first shaper tr A coil voltage, the output of which is connected to the input of the first multi-tap voltage divider and the inputs of the second amplitude comparators block, the inverse trigger output is connected to the input of the second triangular voltage driver, the output of which is connected to the input of the second multi-divider voltage dividers and inputs of the first block of amplitude comparators The trigger input, the control inputs of the first and second triangular voltage drivers, the signal input of the adder are combined and are the input of the frequency multiplier. but. kj ... 4j44-l-4 - + - J I I Editor N.Rogulich Compiled by Y. Maximov Tehred A. Kravchuk Proofreader A.Zimokosov Order 5138/57 Circulation 816 Subscription VNIIPI USSR State Committee on inventions and postcards 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing predirection, Uzhgorod, Projecto st., 4