SU1257867A1 - Redundant pulser - Google Patents

Abstract

The invention relates to digital automation and can be used to synchronize highly reliable computing devices. The purpose of the invention is to improve the accuracy of the generator at high frequencies following output signals. The device contains a master oscillator 1, frequency dividers 3 and majority elements 6. The introduction of reversible counters 4, binary adders 5, asynchronous information bindings blocks 7, decoders 8, elements OR 9 and 10 and the formation of new connections between device elements set goal 3 il. (L from 1 SP 00 o "

Description

The invention relates to digital automation and can be used to synchronize highly reliable computing devices.

The purpose of the invention is to improve the accuracy of the redundant pulse generator at high frequencies of following output signals.

Fig. 1 shows a functional diagram of a redundant generator-p4 pulses; FIGS. 2 and 3 are timing charts of operation.

The redundant pulse generator contains master oscillators 1, input bus 2 reset, dividers 3. frequencies, reversible counters 4, binary -: adders 5, majority element 6, block 7 bindings, asynchronous information, decoders 8, first elements OR 9, second elements Р1ПИ 10, generator input 11.

Figs 2 and 3 denote the input signals of the majority element with asynchronous channels -a, 5, b, the input signal of the majority element with asynchronous channels -, the number reflecting the current status of the bits of the adder - e, the output signal of the master oscillator - e neither the low-order bits of the adder - Y, 1, the state of the highest discharge of the adder and the output signal of the majority element when they are synchronous - and, the output signal of the majority element, and when the phase difference is greater than 67.5 degrees; -k, A, impulse of the asynchronous information binding unit when the signal of the majority element lags; -M, asynchronous information binding unit impulse with the signal phase - n, asynchronous information binding impulse when the signal of the majority element is ahead; correction pulses V , P.

The inputs of the 3 frequency divider are connected to the outputs of the master oscillators 1, and the reset inputs of the 3 frequency dividers are connected to the input bus 2, the outputs of the 3 frequency divider are connected to the first groups of inputs of the adders 5, the second groups of their inputs are connected to the outputs of the reversing c 4, the outputs of higher resolution Yes adders 5 are connected to the inputs of the majority element 6, the output of which is connected to the first inputs of the asynchronous information block 7 and the output. 11 generators, second inputs of blocks

ABOUT

five

five

0

7 bindings of asynchronous information are connected to the outputs of master oscillators 1, groups of code inputs of decoders 8 are connected to the outputs of adders 5, and strobe their inputs are connected to the outputs of blocks 7 of asynchronous information bindings. The inputs of the first elements OR 9 and the inputs of the second elements OR 10 are connected to the outputs of the decoders 8, the outputs of the first elements OR 9 are connected to the inputs of the forward account, and the outputs of the second elements OR 10 - to the inputs of the reverse counting of reversible counters 4, while the inputs reset of reversible counters 4 are connected to the input bus 2 reset.

The redundant pulse generator operates as follows.

The master oscillators 1 clock the remaining nodes. Dividers 3 frequencies reduce the frequency of the master oscillators by 8 times and provide information on the current phase of each channel to the adders 5. Reversible meters 4 are stored and provide information on the magnitude and sign of the phase correction to the adders 5. The adders 5 correct the phase of each channel by the amount of the correction given by the reversing counters 4. The majority element 6 performs a vote on the phase-corrected signals from the adders 5.

Block 7 of asynchronous information binding generates pulses with a duration of one generator period 1, with the fronts of the indicated pulses:. coincide with the positive differences of the pulses of the generator 1.

These pulses are formed after each negative differential signal at the output of the majority element 6, the decoder 8 together with block 7 bindings of asynchronous information and the elements OR 9 and 10 analyzes the phase shift between the signals of the majority element 6 and the bits of the digits of the adder 5 and when transiently shift of a given threshold and generates a correction signal. . Threshold correction is chosen based on the fact that the phase difference of any two channels does not reach the value of 180 degrees, at which the signal of the majority element is distorted. A similar case is shown in FIG. Here, the phase difference between the signals a and 8 is close to 180 degrees and the output signal (d) is majo

the lead element 6 is distorted,

In the example of implementation, the correction threshold is set equal to 67.5 degrees, while even the simultaneous opposite deviation of the phases of two channels by 67.5 degrees from the signal of the majority 2 element gives the phase difference of these channels 135 degrees, ensuring the normal operation of the majority element 6.

The process of forming the correction signals is shown in FIG. When the majority element 6 lags by a large value, the correction threshold (plot K), the impulse of the asynchronous information block 7 (plot m) coincides with the numbers 2 and 3 at the output of the adder 5 (plot d). In this case, the negative correction signal (epyurap) is removed from the output of the first one.

Similarly, the plots of L o, P show the signal of the 6A major element, a pulse of the asynchronous information block 7, and a positive correction signal P, generated when the signal of the major element 6 is ahead. The H pinch of the asynchronous information block is shown. signals of the majority element 6 and the highest section of the adder 5, which does not generate a correction pulse.

After switching on the resected generator and the arrival of a pulse on the input bus 2, the dividers 3 frequencies and the reversible counters 4 are in the zero state.

4P

As the clock pulses arrive from the master oscillators 1, the divided frequency signals appear at the outputs of frequency dividers 3, and at the first moment of the signal phase at the same outputs of frequency 3, the frequencies coincide. In this case (since the reversible counters 4 are in the zero state) the phase of the signals at the outputs of the adders 5 does not differ from the phase of the signals 50 at the corresponding codes of the dividers 3 frequencies.

Then, due to the difference in the frequencies of the master oscillators 1, the phase difference increases and to exceed the correction threshold 55 from the output of the first element. OR 9 or the second element OR 10 to the corresponding input of the reverse impulse

Correction counter.

When a correction pulse arrives at the reversible counter 4, its state changes from the initial 000 to 001 or 111, depending on which input of the reversible counter 4 received the correction impulse, i.e. from zdak correction. 10 Upon receipt of the next correction pulse, the state of the reversing counter 4 changes to 010 (with a positive correction) or 0} (with a negative correction), etc. 15 At the same time, the output signals of the adders 5 become different from the signals of the 3 frequency dividers. For a cycle of recalculating the dividers bits, 3 frequencies are successively taken

element OR states OOQ, 001, 010, 011, 100 110, III,

When the reversible counter is 4 001 or 111, the bits of the adder 5 successively take the values

thirty

 35

respectively

In the revosive counter state, 4 010 or 110 bits of the adder 5 successively take the values

010 or, respectively, and t, d.

on

100 101 ON 111 000 001

I1 000 001 010 011 100 101

momentum arrives

respectively

enrueann-eetii.

In the revosive counter state, 4 010 or 110 bits of the adder 5 successively take the values

010 or, respectively, and t, d.

I1 000 001 010 011 100 101

Thus, when each next pulse of correction is received, the reversible counter 4 signals at all outputs of the adder 5 are shifted by one cycle relative to the corresponding bits of the frequency divider 3. For the higher bit of the adder 5, this means a shift by 1/8 of the period or 45 degrees in the direction of decreasing the phase difference of the signals of the majority element 6 and the higher bit of the adder 5.

The residual phase difference value of 22.5 degrees is permissible from the point of view of normal operation of the majority element 6. After the correction pulse has passed, the phase difference again increases due to the difference in the frequency of the master oscillators 1 and upon reaching 67j5 degrees a correction pulse is issued, the difference phases is reduced to 22.5 degrees, and the process is repeated.

Claims (1)

Invention Formula A redundant pulse generator containing in each of the channels a backup master oscillator and a frequency divider, whose input is connected to the master oscillator output, an input bus of a reset, connected to the reset input of the frequency divider of each of the h channel, and the majority element whom connect Iljinn is not equipped with an output bus, which differs with the fact that, in order to improve accuracy at high frequencies of output pulses, binary cyt iaTop, reversible pulse counter, asynchronous information locking block, decoder, first and second elements are introduced into each of its n channels OR , moreover, the first groups of inputs of adders are connected to the outputs of the frequency divider, the second groups of inputs of adders - to the outputs: reversible; the counter, the output of the higher bit of the adder is connected to the input of the majority element, the output of which is connected to the first input of the asynchronous information binding block of each of the n channels, the second input of the asynchronous information binding block is connected to the output of the master oscillator, the code inputs of the decoder are connected to the outputs the adder, and the gate input of the decoder from the output: the asynchronous information lock block, the first and second inputs of the first and second OR elements are connected to the corresponding DeshiFrator outputs, the output of the first element OR is connected to the input of the forward counting of the reversible counter, and the output of the second element OR to the counting input of the reversible counter; the reset input of the reversible counter of each of the l channels is connected to the reset bus. 0.1 .2.3 .. 5 .6.7,0. 1 .2.3 L.5.6.7 lllllpp lllllg riJTJ JlJ LrLn r P P P L L -. Editor E. Kopcha Compiled by Y.Surov Tehred I. Veres Proofreader M. Sharoshi Order 5042/59 Circulation 765 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab. d.4 / 5 Production and printing company, Uzhgorod, Projecto st., 4 t t t t t P L -.t t t Fig.Z