SU1257655A1 - Interface for linking electronic computers with peripherals - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in computer systems for the exchange of information between computer groups and external devices. The aim of the invention is to expand the class of tasks to be solved by solving problems, initiating the exchange both from the computer and from external devices. The goal is achieved by the fact that a device containing a column selection block and a polling pulse generator are introduced into a device containing a matrix of switching units, two groups of interface matching blocks and a group of row selectors. 3 з.п, ф-л, 4 Il.

Description

The invention relates to computer technology and can be used in computer systems for the exchange of information between electronic computers (VM) and external devices (subscribers-BA),

The aim of the invention is to expand the class of tasks of the device.

FIG. 1 is a block diagram of the device; in fig. 2 - functional circuit of the switching unit; in fig. 3 is a block selection block diagram; in fig. 4 is a block selection diagram of a line.

The device contains (Fig. 1) matched blocks 1 for matching with the first and second interface groups, switching blocks 2, group column selecting blocks 3, group row selecting blocks 4 and generator 5, polling pulses, information lines 6 and 7 - control outputs and inputs (interface on the VM side), lines 8 and 9 of information control outputs and inputs (interface on the VA side), line 10 of column availability (STLB ON signals), column selection lines 11 (SIGNAL signals). STLB), lines 12 readiness lines H signals PAGE. - ON), lines 13 of row selection. (Signals CONNECT. PAGE), lines 14 of reset (signal CBP. CTP), lines 15 of row sampling (signals FBG PAGE), lines 16 of column selection signals VBR STLV), line 17 enable column polling (ONOPR.STLB signal ON), line polling enable line 18 (OPPR.STR signal ON) 4 lines 19 of column polling pulses (OPR signals; STLB) - line 20 polling polls (OCR signal).

The matrix switching units 2 (FIG. 2) consist of a trigger 21, elements And 22 and 23 of the first and second groups, element 24 and two elements of development 25.

; The column selection block 3 (Fig. 3) contains a trigger 26, a decoder 27, the first 28, the second 29, the third 30, the fourth 31 and the fifth 32 elements AND, the first 33 and the second 34 elements SH, first 35 and the second 36 elements are NOT and the elements of 37 are separate. Block 4 line selection (Fig. 4) contains a trigr 38, a decoder 39, the first 40, the second 41, the third 42, even

Vertical 43, Fifth 44, Sixth 45 Elements AND, First 46 and Second 47 Elements OR, First 48, Second 49, Third 50 and Four 51 Elements NOT

and elements of 52 razkki.

Interface matching blocks 1 These are sets of amplifier-receivers and amplifiers-transmitters intended to be matched to

 the physical level of the elements of blocks 2,3 and 4 devices with interface lines between VM and VA. Generator 5 polling pulses in the presence of enabling signals ON.OPR. STLB, ON.OPR.

The MFR provides for the corresponding lines 19 and 20 of the sequence of pulses OPR.STLB or OPR.STR.

The VM-VA interface may correspond, for example, to the standard EC-computer I / O interface.

The device works as follows.

In the initial state, the triggers 21 of the blocks 2 are in the zero state of the scientific research institutes and the elements AND 22, 23 are blocked,

which break lines of interfaces

VM-VA. In the zero state are

also triggers 26 and 38 of blocks 3 and 4.

Exchange of information on the initiative

VM between, for example, the jth VM and the ith VA begins with the issuance by the VM via line 6 of the address of the selected VA and the corresponding identification signal, which are fed to the inputs of block 3j

and a decoder 27. At the same time, the signal from the corresponding output of the decoder 27 is fed to isolation element 37 and to line 15 of the signal of the FBG.STR of the i-th line, as well as through the element OR 34

line 37, line 17

the ON signal and the generator input 5. If by this time, there is an enabling signal — no impulse OPR. TSLLB on line 19, then the trigger 26 is set to And the Single state and allows the impulse OPR.STLB to pass from line I9 through elements AND 29 and OR 33 on line 11 of the signal

 column, simultaneously blocking the passage of pulses OPR.STLB through the element And 32 on the following blocks 3.

The SUBSTITUTE signal is present on line 11 and prepares elements AND 24 of all blocks 2 of the specified columns, including block 2 of the i-th row, to the other input of the element AND 24 of which received a signal CONSTRUCTURE along the line

ten

15

31257655

 from the block Ai, where it was formed on the elements OR 46, AND 40, NOT 48 by the signals of the PAGE ON from the line 12 and by the signal in the center received on the line 15 from the block 3j. Thus, block 2 is selected in the Jth column and i-th row, the trigger 21 of which is set to one and allows information passing through the interface lines between the corresponding VMs and ONs through the AND 22, 23 elements. to the VM ends with the issuance of a logical connection signal given by the VA, at which the VM removes the identification signal of the address and the address of the selected VA and starts the exchange of information with the i-th VA. The logical connection signal i-ro BA also enters via line 7 to block 3j on element 20 And 30, allowing reset to the zero state of trigger 26, and also goes to block 41 on input of element NO 50, blocking an output signal CUR. And 45 before the end of the Operation with this. WA. After the exchange and removal of the logic signal BA is completed, the flip-flop 21 of the block 21j is reset by the CBP.STP signal outputted on line 14 by the AND element 45 of the block 41.

If several VMs simultaneously initiated I / O operations and inserted the address codes necessary for the exchange of VA to the corresponding lines 6, the triggers 26 in the corresponding blocks 3 are set to one. The logical connection of the VA and the VM in this case is carried out alternately in accordance with the priority of blocks 3 along the line 19 of the OFR.STLB pulses. An attempt of a VM is connected to an already connected VA, blocked by a PAGE ON signal, issued by trigger 21 of the corresponding block 2 through 25

thirty

35

45

block

The cut element 25 is separated by line 12 to the corresponding block. 4 at ele. COP NOT 48.

In the case of a VA initiative, the establishment of a connection, for example, between the i-th BA 50 and the J-th VM, starts with the address VA of the VM address and the subscriber demand signal on line 8 in block 4i, where the VM address is decoded. The operation of the elements of block 41 to provide a logical connection -55 of the 1st VA is similar to the operation of the corresponding elements of block 3; in the block 2iJ, the signal of the requirement of the 1st VA is output to the jth VM and the logical connection is completed by issuing the logical connection signal 1- th VA in the j-th VM, which enters in block 41 on the element And 42, allowing reset trigger 38.

When simultaneously requesting several VA signals, the logical connection of the VA is carried out alternately in accordance with the priority of the blocks 4 along the line 20 of the OPD pulses. PAGE Attempting a VA is connected to a VM that is already working with another VA is blocked by a STLB ON signal issued by the trigger 21 of the corresponding block 2 via the isolator 25 on line 10 to the corresponding block 3 for the HE 35 element.

In order to ensure the resolution of conflicts with simultaneous testing of VA and VM, to initiate an I / O operation, the SCR pulses are shifted relative to the CRC pulses by the time required for the STLB.VCL signals in the 10 lines or the PAG.VCL signals 12 lines.

Claims (1)

Invention Formula 1. A device for interfacing electronic computers with external devices containing the first group of interface matching units, the first inputs and outputs of which are connected respectively to the information and control outputs and the inputs of the corresponding electronic computing machines, the second group of blocks matching the interfaces whose first inputs and outputs are connected by COOT. Correspondingly with information and control outputs and inputs of the corresponding external devices, a matrix of switching units and a group of row selectors, the second input and output of the 1st interface matching unit of the first group (, M) and the second input and output of the j-ro interface matching unit the second group (, N) are connected respectively to the first and second information outputs and inputs of the switching unit of the 1st row and j-ro column of the matrix, the readiness output of the row and the input sample of the row of which are connected respectively to the readiness input and in razresannoy vshge course. After the implementation of the 1st block selection group 10 15 20 0 25 thirty five mutations in block 2iJ, the signal for the requirement for the 1st VA is outputted to the jth VM, and the logical connection is completed by issuing the 1st VA logic connection signal to the jth VM, which also goes to block 41 on AND 42, allowing flush trigger 38. When simultaneously requesting several VA signals, the logical connection of the VA is carried out alternately in accordance with the priority of the blocks 4 along the line 20 of the OPD pulses. PAGE Attempting a VA is connected to a VM that is already working with another VA is blocked by a STLB ON signal issued by the trigger 21 of the corresponding block 2 via the isolator 25 on line 10 to the corresponding block 3 for the HE 35 element. In order to ensure the resolution of conflicts with simultaneous testing of VA and VM, to initiate an I / O operation, the SCR pulses are shifted relative to the CRC pulses by the time required for the STLB.VCL signals in the 10 lines or the PAG.VCL signals 12 lines. Invention Formula 1. A device for interfacing electronic computers with external devices, containing the first group of interface matching units, the first inputs and outputs of which are connected respectively to the information and control outputs and the inputs of the corresponding electronic computers, the second group of blocks matching the interfaces whose first inputs and outputs are connected by COOT. Correspondingly with information and control outputs and inputs of the corresponding external devices, a matrix of switching units and a group of row selectors, the second input and output of the 1st interface matching unit of the first group (, M) and the second input and output of the j-ro interface matching unit the second group (, N) are connected respectively to the first and second information outputs and inputs of the switching unit of the 1st row and j-ro column of the matrix, the readiness output of the row and the input sample of the row of which are connected respectively to the readiness input and in move $ 12 solvable so that, in order to expand the class of tasks of the device through the organization of the initiative exchange both from the computer and from the external devices, a polling pulse generator and a group of column selection blocks are entered into it, and the information outputs of the row selection blocks are connected to the second outputs of the interface group matching blocks of the first group, the information and gate inputs of the group selection block j-ro are connected respectively to the second output j-ro the second group interface matching unit and the outputs of the j-ro switching units of the matrix column, the column sampling inputs and the readiness output of the column are connected respectively to the resolution output and the input ready J-ro of the group column selection block, the reset inputs of the switching blocks of the i-th row of the matrix are connected to the reset output of the i-ro group row selection block, whose interrogation input is connected to the interrogation output (il) -ro of the group row selection block and the enable input with 1 outputs of sampling the row of the group column selection blocks, the enable input J-ro of the column selection block of the group is connected to the JM output of the column selection of the sampling blocks, group rows, readiness outputs of which are connected to the onpiocoB polling input enable input, first and second outputs Which are connected respectively to the polling inputs of the first row selector and group column, and the input of the polling column to the readiness outputs of the column selector blocks, the polling input J-ro of the column selector block of the group is connected to the output: polling (jl) -ro of the column selector groups. . 2, The apparatus according to claim 1, 1, and 19, which is that the column selection block contains a decoder, the input of which is the information input of the block, a trigger, five elements AND two elements OR, two elements NOT, an isolation element and a group isolating elements, the output of the first OR element is the output of the block resolution, and the first and second inputs are connected respectively to the outputs of the first and second AND elements, the first inputs of which are corresponding the readiness and polling inputs, the second input of the first element is NOT connected to the block enable input, the first input of the third element is AND through the second element NOT to the polling input of the block, the second input is connected to the gate input of the block, and the third input is connected to the second input The second element And the direct output of the trigger, the reset input and the installation input of which are connected respectively to the outputs of the third and fourth elements And the first input of the fourth element And is connected with the output of the second element is NOT, and the second input is with the output of the second element OR, and through the isolating element with the output of the blocking output, the first, second inputs and output of the fifth element AND connected respectively with the inverse trigger output, the block polling input and the block polling output, the group of outputs of the decoder is connected to the input group of the second element OR and through the group's bridging elements to the corresponding block row sample outputs. 3. A device according to claim 1, characterized in that the row selection block comprises a decoder, a group of isolation elements, two OR elements, a trigger, four NOT elements and six AND elements, the output and the first and second inputs of the first OR element are connected respectively with the block row sample output and the outputs of the first, second AND elements, the first inputs of which are the block resolution and interrogation inputs respectively, the reset and setup trigger inputs are connected to the third and fourth AND outputs, respectively, and the inverse output - to the first input of the fifth element AND, the output of which is the polling output of the block, and the second input is connected to the polling input of the block, the second input of the first AND element is connected through the first element NOT to the readiness input of the block and the first input of the sixth And element, the output connected to the block reset output, the first inputs of the third and fourth elements I are connected via the second element NOT to the polling input of the block, the second inputs respectively to the forward output of the trigger and the output of the second OR element, the group of inputs of which is connected to the group outputs of the decoder and through the elements of isolation with. the block sampling outputs, the output of the second element OR is connected through the isolating element to the output of the block readiness, the input of the decoder is connected to the information input of the block, the third input of the third element AND, and the third element NOT to the second input of the sixth element AND, the third input of which the fourth element is NOT connected to the block resolution input, the direct trigger output is connected to the second input of the second element I. 4. The device according to claim 1, about tl and - the fact that the switching unit contains two groups of elements five And, the element And, the trigger and two elements of isolation, the first inputs of the elements of the first and second groups are connected respectively with the first and second information inputs of the block, the outputs with the second and first outputs respectively, and the second inputs with the forward output of the trigger and the inputs of the first and second isolation elements, the outputs of which are respectively the outputs of column readiness and row readiness of the block, the reset input and the trigger setup input are connected respectively to the block reset input and the output of the AND element, the first and second the inputs of which are respectively the inputs of the selections. ra row and column select block. ffUf-g 7J 12 15 g & 20 fS 76f 16ff leg. eight r