SU1305699A2 - Interface for linking electronic computer with peripheral equipment - Google Patents

Abstract

The invention relates to computer technology and can be used in computer systems for interfacing a common resource of external devices with a computer. The purpose of the invention is to reduce the loss of time during computer calls at incorrect addresses of external devices. The goal is achieved by the fact that the sixth element 54 and the third element NOT 53 are entered into each column selection block. If the address of the selected subscriber is incorrectly specified because of a program error or a malfunction of the interface address buses, the signal returns via line 7 to the computer through the open element 54. 4 il. MS)

Description

The invention relates to computing, can be used in computing systems for linking the common resource of external devices - subscribers (BA) with electronic computers (VM), and is an improvement of the device according to the author. St. No. 1257655.

The purpose of the invention is to reduce the loss of time when addressing incorrect addresses.

FIG. 1 shows a block diagram of the proposed device; Fig.2-4 functional diagrams, respectively, of switching units, column selection and row selection.

The device contains (Fig. 1) the matched blocks 1 for matching the interfaces of the first and second GROUPS, switching blocks 2, blocks 3 for selecting columns, blocks 4 for selecting group lines, generator 5 for polling pulses, lines 6 and 7 for information outputs and inputs (interface from the computer), lines 8 and 9 of information outputs and inputs (interface from the BA), -10 column availability (signals STLB.ON), column selection lines 11 (signals CONNECTED POST), readiness lines 12 lines (signals p. on.), lines 13 select lines (signals CONNECT LINE), lines 14 reset (si drove SVR.STR.), line 15 of sample rows (FBG.STR signals), line 16 of sampling columns (FBG signals. STLB.), line 17 of the inclusion of column polling (signal ON.OPR.STLB.), line 18 of inclusion of polling lines (the signal of the VALUE DISABLATION ON), the lines 19 of the polling columns of the columns (signals ODA, STLB.) and the lines 20 of the pulses of the polling of the lines (the signal OPR.SED.).

The matrix switching units 2 (Fig. 2) consist of a trigger 21, elements 22 and 23 of the first and second groups, element 24 and two elements of the 25 isolation.

The column selection block 3 (FIG. 3) contains a trigger 26, a decoder 27, the first 28, the second 29, the third 30, the fourth 31 and the fifth 32 And elements, the first 33 and second 34 OR elements, the first 35 and second 36 NOT elements and elements of 37 interpretations.

Block 4 line selection (figure 4) contains the trigger 38, the decoder 39, the first 40, the second 41, the third 42, the fourth 43, the fifth 44 and the sixth 45 elements And, the first 46 and second 47 elements OR, the first 48, the second 49 , the third 50 and fourth 51 elements are NOT, the elements are 52, the third element

NOT 53 and the sixth element And 54.

The interface matching units 1 are sets of receiver amplifiers and transmitter amplifiers for matching on

the physical level of the elements of blocks 2-4 of the device with the lines of the interface between the VM and the VA. Generator 5 polling pulses in the presence of enabling signals VL.OPR.STLB., VOL.OPR.STR. It follows the corresponding lines 19 and 20 of the sequence of pulses of the OPD. STLB or OPD.

The VM-VA interface may correspond, for example, to the standard EC-computer I / O interface.

The device works as follows.

In the initial state, the triggers 21 of the blocks 2 are in the zero state and block the elements AND 22 and 23, which disconnect the VM-VA interface lines. The triggers 26 and 38 of blocks 3 and 4 are also in the zero state.

Exchange of information on the initiative

VM between, for example, the j-th HV and the i-th VA begins with the VM through line 6 of the address of the selected VA and the corresponding identification signal,

which arrive at the inputs of the corresponding block 3 and the decoder 27. At the same time, the signal from the corresponding output of the decoder 27 goes to the isolator 37 and to the corresponding line 15 of the row, as well as through the OR element 34 to the isolator 37, line 17 of the signal ON. OPR. and to the input of the generator 5. If by this time there is an enabling signal - no pulse

OPR. on line 19, then the trigger 26 is set to one and allows the passage of the pulse. from line 19 through items

And 29 and OR 33 to signal line 11

SUBSCRIBE. j-ro column, simultaneously blocking the passage of pulses OPR.STLB. through the element And 32 and the following blocks 3.

Signal CONNECT. is present on line 11 and prepares elements AND 24 of all blocks 2 of a given column, including a block of 2 rows, on another

element input AND 24 which receives a signal CONSTR. on line 13 with block 4., where it is formed on the elements OR 46, AND 40, NOT 48 by the PAGE signals. ON from line 12 and the FBG-STR. signal received on line 15 from block 3. Thus, block 2 is selected in the JM column and i-th row, trigger 21 of which is set to one and resolves through AND 22 and 23 passing information through the interface lines between the corresponding VM and VA. The logical connection procedure BA and BM ends with the specified BA signal of the logical connection, by which the VM removes the identification signal of the address and the address of the selected VA and starts information exchange with iM BAJ The logical connection signal i-ro BA also goes through line 7 to block 3J on element 30, allowing the reset to the zero state of trigger 26, and also entering block 4- on the input of element 50, blocking the output of the CBP signal, from element 45 until the end of the operation with this VA. remove VA signal logic The second connection is made to reset the trigger 21 of the block 2-; signal SVR.STR., installed on line 14 element AND 45 block 4.

If several VMs simultaneously initiate I / O operations and issue the address codes necessary for the exchange of VA on the corresponding line 6, then the triggers 26 in the corresponding blocks 3 are set to one. The logical connection of the VA and the VM in this case is carried out alternately in accordance with the priority of the blocks 3 along the line 19 of the RAB STBL pulses. An attempt by the BM to connect to an already connected VA is blocked by the EXP. PAGE signal outputted by the trigger 21 of the corresponding block 2 via the 25 isolator on line 12 to the corresponding block 4 on the NE 48 element.

Attracting the non-correct address code BA (BA with this address is missing) at the outputs of the decoder 27 of block 3 and the output of the element OR 34 there are no signals and setting the trigger 26 to one state is not performed. At the same time, at the input of the element I 54, the resolution level is established, output from the element NO 53. With the entrance to the group of inputs of the element 54, the sampling signal from the VM channel and the address identification signal, a subscriber sampling signal is generated at its output, which comes through the corresponding output of block 3 - to the subscriber's sample signal line to the BM channel, which initiated the input-output operation, providing the possibility of identifying this situation with incorrect setting of the address BA.

In the case of a VA initiative, the establishment of a connection, for example, between the i-th VA and JM of the VM, begins by issuing the VA address of the VM and the subscriber demand signal via lines 8 to block 4, where the BM address is decrypted. The operation of the elements of block 4 to ensure the logical connection of i-ro VA is similar to the operation of the corresponding elements of block 3. After switching is performed in block 2 .. the i-ro VA request signal is output to the jth VM and the logical connection procedure ends with a higher logical connection signal given VA in the j-th VM, which enters in block 4 on the element I 42, allowing the sbrbs of the trigger 38.

When simultaneously demanding signals of several BAs, the logical connection of the VA is made alternately in accordance with the priority of the blocks 4 along the line 20 of the pilot waves. PAGE An attempt to connect a BA to a VM that is already working with another VA is blocked by the STLB ON signal, issued by the trigger 21 of the corresponding block 2 through the isolator 25 on line 10 to the corresponding block 3 on the HE 35 element.

To ensure the resolution of conflicts when BA and VM are simultaneously attempting to initiate an input operation, a VPSLT pulse will occur. shifted relative to the pulses OPR.STR. for the time it takes to establish the STLB.BLK signals in the lines 10. or in lines 12 of the signals.

Claims (1)

Invention Formula A device for interfacing electronic computers with ext. them devices auth. St. No. 1257655, characterized in that, in order to reduce the loss of time when accessing incorrect addresses, you are assigned to each block in it 513056996 the sixth element OR of the same column selection block, and the third element are NOT entered, the input group and the output of the sixth element AND j-ro of the selection block with the second information output and the column (, N) are connected via the third input j- The ro block of the matching inter-element is NOT with the output of the second element 5 of the second group of faces. m L1 7 22 W10 12 ( 2 --t eleven Compiled by V. Vertlib Editor N. Gunko Tehred A. Kravchuk.   .one. g .. ZakGiZZM Circulation VNIIPI State Committee uLLF for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production printing company, Uzhgorod, Projecto st., 4 11 3 ; v FIG. 2