SU1254430A1 - Device for measuring amplitude of oscillations of balance of mechanical timepiece - Google Patents

Abstract

The invention relates to watch making and allows iioBb to measure measurement accuracy. The device consists of a sound signal sensor 1, an amplifier 2, a detector 3, comparators 4 and 10, a source 5 of the reference voltage, a trigger 6, a multivibrator 8, a sawtooth voltage generator 9, a front isolation circuit 11, drivers 12 and 14 to them

Description

pulses, OR circuit 13, delay line 15, resetting counter 16, reference frequency source 17, memory register 18, memory-compatible comparator 19, programmable read-only memory 20 and display 21. Introduction of new elements and the formation of new The sow between the elements of the device allows the amplitude values obtained to display

The invention relates to a watch instrument making industry and can be used to control the amplitude of oscillations of a balance of clocks in automated control systems.

The purpose of the invention is to improve the measurement accuracy.

FIG. 1 is a block diagram of a device for measuring amplitude.

dy oscillations balance mechanical watches; in fig. 2 - time diagrams showing the operation of the device; in fig. 3 block diagrams with edge detection, pulse driver, and logical block OR.

The device consists of audio signals sensor 1 (microphone), amplifier 2, detector 3, the output of which is connected to the first input of the first comparator 4, the second input of which is connected to the source 5 of the reference voltage, and the first comparator 4 connected to the first input of the trigger 6, the output of which is connected to the first input of the logic circuit AND 7, the starting input of the waiting multivibrator 8 and the starting input of the sawtooth generator 9, the output of which is connected to the second input of the second comparator 10, the first the input of the second comparator 10 is connected to the output of the detector 3, and the output of the second comparator 10 is connected to the first input of the edge extraction circuit 11, the outputs of which are connected through the second pulse generator 12 to the inputs of the logic circuit OR 13, and the second reset input of the selection circuit 11 is connected to the second

on the display 21 in the form of a row of lines, as well as the number of measurements, since the number of measurements is equal to the number of pulses arriving at the recording input of the display 21. If the measured value of the amplitude of balance oscillations goes beyond the tolerances, then the corresponding line of the display 21 will display that the amplitude is not included in the tolerance. 3 il.

five

0

reset the input of the generator 9 sawtooth voltage, the second reset input of the trigger 6, the output of the first driver 14 pulses, the input of which is connected to the output of the waiting multivibrator 8, and the output of the first driver 14 of the pulses connected to the input of the delay line 15 and the reset input of the counter 16, the counting input which is connected to the output of the logic circuit And 7, the second input of which is connected to the output of the source 17 of the reference frequency, and the outputs of the counter 16 are connected respectively to the inputs of the memory register 18, the recording input of which It is connected to the output of the OR 13 logic circuit, and the outputs of memory register 18 are connected respectively to the inputs of a digital comparator 19, the outputs of which are connected to the address inputs of a programmable permanent memory unit 20 (PROM), and the outputs of a block 20 are connected to information inputs of a display 21 A recording input is connected to the output of the delay line 15.

The device works as follows.

Noises (sound packets), arising during the operation of the anchor descent of the clock mechanism, are sensed by the sensor 1 of sound signals (microphone), which are converted into electrical signals of the clock, and fed to the input of amplifier 2, which has automatic gain control. The amplified signals from the output of the amplifier 2 (Fig. 2a) are fed to the input of the detector 3. The detector

3 represents a standard unit and is built according to a precision rectifier circuit with a capacitive filter at the output. The introduction to the detector device 3 is due to the need to protect the device from the effects of impulse noise between the pulse packets of the clock. When choosing the detector filter time constant is longer than the time of the random impulse noise, the amplitude of the latter is significantly reduced, which leads to a more reliable response of the first comparator 4 from the effect of the release noise pulse (N - and the clock pulse). From the output of the detector 3, the detected signals (pulses) of the clock (Fig. 2S) arrive at the first input of the second comparator 10 and at the first input of the first comparator 4. Received leading edge of the release noise pulse (first clock pulse)

from the output of the detector 3 to the first input of the first comparator 4 is compared with the reference voltage UQI, coming from the output of the source 5 of the reference voltage. At the moment of comparing the leading edge of the release noise pulse with the reference voltage Uon, at the output of the first comparator 4, a positive output voltage drop occurs, which transfers the first trigger 6 through the first input. The trigger 6 records the beginning of the formation of the time interval between the first and third pulse of the clock. The source 5 of the reference voltage is a standard block. The magnitude of the reference voltage is selected from the condition of ensuring the maximum noise immunity of the first comparator

4 in the intervals between the packets of impulses of the clock. When choosing the magnitude of the reference voltage Udn (0.15 - 0.2) and, „a, e) (where an, is the maximum amplitude of the release noise pulse), the detected random noise pulses fall into the dead zone of the first comparator 4. When exposed, the trigger 6 positive voltage drops from the output of the first comparator 4, the latter overturns and proceeds to the output

to state 1. Trigger 6 is the D-trigger. Trigger 6 is transferred by the leading edge of a pulse at the first input (synchronization input c), D is constantly triggered by trigger 1, reset is triggered by the second reset input (R-input), the voltage level corresponding to level O. Since the D-input of the trigger 6 is constantly set to 1, with the arrival of a positive differential (the leading edge of the pulse), from the output of the first comparator 4 to the first input of the trigger 6, the latter is set to exit to state 1 and saves this state whatever m addition, there are present at the first input of further voltage pulses, or not, until the arrival of the second resetting input of the flip-flop 6 negative pulse (output from the first pulse shaper 14), i.e. the pulses that occur when the voltage goes from 1 to 0 and dreams to 1. From this point on, trigger 6 is again ready for operation. When the trigger 6 is set to exit to state 1, the leading edge of this differential (the leading edge of the trigger pulse 6, Fig. 26) simultaneously starts the waiting multivibrator 8 (Fig. 2d) and sawtooth generator 9 (Fig. 2). The output of the trigger 6 is connected to the start input of the waiting multivibrator 8 and the start input of the generator 9 sawtooth voltage. Simultaneously with the launch of blocks 8 and 9, the first input of the logic circuit And 7 is set to level 1. The pulses of the reference frequency ign from block 17 begin to pass through the logic circuit And 7 to the counting input of the counter 16. The counter 16 starts counting the pulses of the reference frequency during equal to the duration of the rectangular impulse formed at the output of the trigger 6. When starting the waiting multivibrator 8, a rectangular impulse is formed at its output (Fig. 2d) with the duration

,

T „/ 2 8

nominal half-period of balance fluctuations; a value that determines the maximum allowable deviation of the current half-period from its nominal value.

This pulse determines the duration of the presence of trigger 6 in state 1. The waiting multivibrator 8 is completed in accordance with. The standard circuit. A formulated rectangular pulse from the output of the multivibrator 8 is fed to the input of the first driver 14 pulses, after the pulse expires, the back edge of the pulse at the output of the first driver 1,4 forms a short negative pulse (FIG. 2a) j which goes to the second emitters. the inputs of the trigger 6, the sawtooth voltage generator 9, the edge isolation circuit 11 and the counter 16 both return these blocks to the initial state, and also enter the enable input for the communication of the PIZU block 20 and od line delay 15, pulse generator 14 is constructed to AND-NO elements by the standard procedure.

Run generator 9 sawtooth

Voltage occurs almost simultaneously with the arrival at the first input of the second KONmapaTopa 10 detected pulse code clock, and the beginning of the formation of a linearly increasing sawtooth voltage at the output of block 9 coincides with the arrival at the first input of the second comparator 10 of the leading edge of the detected pulse, release noise from the detector output 3. A linearly increasing 9 sawtooth voltage generator is built according to a standard circuit based on an analogue integrator with an analog key operating on its operation MOS transistor in the negative feedback integrator. Starting and resetting the integrator: The analogue switch fia of the MOS transistor is implemented by applying triggering or resetting voltages to the gate of the transistor. At the integrator input, a constant potential U, is applied, as a result of integrating a constant value

Neither input, output generated

a pinch of sawtooth tension. From the output of the generator 9, a linearly increasing sawtooth voltage is supplied to the second input of the second comparator 10. Comparison moments of 55 amplitude of the linearly increasing voltage from the output of block 9 and detected} tpuls of the clock from the output tto 15 20

five

0

five

Unit 3 is fixed by the second comparator 10, while the second switch fixes the moments of comparison of both the leading edge of each pulse with a linearly rising voltage, and the decline of each pulse with a linearly rising voltage (Fig. 2)). Since the linearly rising voltage from the output of the generator 9 is a reference for the second comparator 10, when choosing a certain value of the tilt angle. This voltage of the comparator 10 captures the moments of intersection of the pulse of the clock with the linearly increasing voltage of the reference voltage. When the linearly increasing reference voltage of each pulse of the clock in the packet crosses the output of the second comparator 10, a positive pulse is formed, the leading edge of which in time corresponds to the leading edge of the pulse. The number of these positive pulses from the output of the second comparator 10 is equal to the number of travel pulses entering the packet and arriving at 1x to the first input of the second comparator 10. According to the chosen criterion, the last of these positive pulses is a pulse whose leading edge corresponds to the leading edge of the third pulse the clock.

In the case when the time interval i between the 1st and 3rd pulses of the clock is equal to the average value

Wed 7

ramp value

the voltage at this moment is equal to the amplitude of the first pulse (release noise pulse), i.e. U min norm by them From here the angle of inclination ot is determined from the relation:

0 (,. arctg

and imp

-Jcp

where u, j, f | - average value, amplitude of the first pulse of the clock;

wed

- с.ре.цнее value of a time interval between the 1st 3 rd impulses of a course of hours.

On the other hand, the angle of inclination of the linearly increasing voltage is determined by the parameters of the integrator included in the structure of the sawtooth 9 generator 9, and is determined from the relation:

OS, arctg

RC

where Ujj is the constant potential of the voltage entering the input

Integrator: RC is the integrator time constant.

Thus, the desired angle of inclination of C is set by adjusting the value of Qn and the parameters of the integrator R and C.

The remaining remaining pulses of the clock in time after the third pulse, as well as random pulsed interference between the packets of the pulse pulses, do not trigger the second comparator 10, and therefore fix them last, because the amplitude of the remaining pulse pulses of the clock is less than the amplitude of the third pulse and does not exceed linear the increasing reference voltage at the second input of the second comparator 10 at the time of their occurrence, since the threshold of the operation of the comparator 10 increases continuously (linearly) with time (Fig. 2), and the random impulses The interference between the packets of the pulse of the clock due to the high threshold voltage at the second input of the second comparator 10 falls within its sensitivity zone (Fig. 2g). In some cases, the second pulse of the clock (noise pulse) can be comparable in amplitude with the third pulse, but this does not entail a decrease in the reliability of the third pulse, since the leading edge of the last fixing pulse from the output of the comparator 10 still falls on the third pulse the course of the clock and the conditions for the existence of the identification criteria are not violated. Positive pulses from the output of the second comparator 10 are fed to the first input of the front-side 11 of the circuit, which highlights the leading edge of each positive pulse received from the second comparator 10. The edge-separation circuit 11 is a known circuit (Fig. 3) and consists of -triggers and (p-1) logic circuits I.S-triggers on output through logic circuits And are connected in series. The first input of circuit 11 is connected to C - the input of the first trigger and through the circuit AND to other C-inputs of the rest

44308

flip-flops, R-inputs of flip-flops are combined and connected to the second dropoff, and to it the input of the edge isolation circuit 11. When the first positive pulse arrives from the output of the second comparator 10 on the circuit 11, the leading edge of this pulse, corresponding to the leading edge of the first pulse of the clock, tilts

0, the first trigger T is set at its output level 1. This level permits the passage of a second positive pulse from the output of the comparator 10 to the input of the second trigger 5 T. The second impulse with the leading edge overturns the trigger T, sets it to the output in state 1. The first trigger T, to the second positive impulse from the output

0 comparator 10 does not respond, because;: and its input is constantly turning on 1, this also applies to the rest of the triggers. After tilting the second flip-flop T, a level 1 appears at its output, which permits the passage of the third positive pulse through the AND circuit to the input of the third flip-flop T, etc. Thus, the triggers of the allocation circuit 11

The fronts successively in time (alternately) turn over the front fronts of the positive pulses arriving from the output of the comparator 10, and fix the front fronts of the pulses. Setting the circuit 11 to its original state (preparing for the new measurement of the amplitude of balance oscillations) is carried out by applying a short negative pulse.

 ca from the output of the first driver 14 pulses to the second reset input of the circuit 11 (reset of flip-flops T, - T, by R - inputs). The number of flip-flops

five

45

circuit 11 determines the probable number of positive pulses

from the output of the second comparator 10. Taking into account the fact that, in the designated pulse packet, the clock travels to the third pulse inclusively

there may be more than five, among which there are three main and two additional ones superimposed on the release noise and the noise of the pulse, the number of trigers is equal to five. Thus, the number of outputs of circuit 11 is equal to P (in this case, ti 5), each output of circuit 11 sequentially changes its potential in time (from

O in 1) in accordance with the arrival of pulses from the output of the comparator 10. The outputs of the edge detection circuit 11 are connected to the inputs of the second driver 12 pulses. On and outlets of the driver 12, at the moments of flip-flop triggers (from 0 to 1) of the circuit 11, short negative pulses are formed, shifted in time relative to each other.

Block 12 may consist of mill-; Dart pulse shapers based on AND-NOT logic circuits. Each pulse shaper generates a short negative pulse at the output when a positive voltage drop is applied to its input (from 0 to 1). The outputs of the second block of pulse shaper 12 (ti outputs) (Fig. 3) are connected to the inputs of the logic circuit OR 13. On the output of the circuit, OR 13 sequentially shifted relative to each other appear. short negative pulses (Fig. 2j.), the number of which is equal to the number of positive pulses from the output of the second comparator 10 and the corresponding leading edges of positive pulses in time. The last negative pulse from the output of the OR 13 circuit is the pulse corresponding in time to the leading edge of the third pulse of the stroke. hours The sequence of pulses from the output of the circuit OR 13 is fed to the input of the record of register 18 of the memory. Upon the arrival of each negative pulse at the input of the memory register 18 to the last, information is recorded in a binary parallel code from the outputs of counter 16. Since counter 16 receives the first pulse of the clock (trigger 6 is set to state 1, allowing the passage of reference frequency pulses from the output of the generator 17 through the circuit E 7 to the input of the counter 16) starts counting the pulses of the reference frequency, then by the time each pulse arrives at the input of the register 18 of the memory, the counter 16 is i; the number of pulses in the binary code, propori (ionic time of the first short negative pulse from the output of the OR 13 circuit (corresponding to the rising time of the leading edge of the first pulse of the clock) and each subsequent pulse

: ohm from the output of the circuit OR 13. Since the last pulse from the output of the circuit of RSHI 13 is the pulse corresponding to the leading edge of the third pulse of the clock, by the time it arrives at the input of the memory register 18, the counter 16 passes the number of pulses N 1

on

(Fig. 2m)

ten

15

20

25

thirty

35

40

45

50

and proportional to the time interval between the first and third pulse of the clock (Fig.). This M number, represented in the binary parallel code and present at the inputs of memory register 18, is finally rewritten by the last pulse from the output of the IZH 13 circuit to block 18 (the counter outputs are directly connected to the inputs of memory register 18). The number of outputs of the counter 16 (width) and, accordingly, the number of inputs and outputs of block 18 is determined by the maximum number of reference frequency pulses i (, n, filling the time interval T (in the general case, the number of outputs can be denoted by q). Since the number of pulses, passed to counter 16 in time C, proportional to the value of Eo f, the latter value affects the sampling error arising when measuring the time interval by a digital method. Memory register 18 is a standard block and is built on a universal s registers working in the mode. Recording a parallel binary code.

After the 16th number is written to the counter, N continues counting the pulses of the reference frequency until a negative pulse appears at its second drop input. The counter T6 zeroes the i-C outputs of block 18, the number N proportional to t arrives at the outputs of the digital comparator 19. At digital comparator 19 The obtained value of N in the binary parallel code is compared with the settings presented also in the binary parallel code

N

and N

When choosing

min An additional max. dsd of a certain value of the reference frequency IQI is between, a, and the number written in the binary parallel code in memory register 18, and the time t has a one-to-one connection, i.e. a certain number N corresponds to a certain value c.

If we go from the value to the corresponding value of the amplitude of balance oscillations, using the formula:

(R

 An

. 51 G | Where

9 -L.

- amplitude of balance oscillations;

constructive angle of raising balance 5

TD - the nominal period of balance fluctuations;

 - the time interval between the 1st and 3rd pulses of the clock,

then between the number N written to the memory register 18 and the value of the amplitude of the balance oscillations is established as

the connection is unambiguous. In this case, the last formula can be rewritten as follows:

P

2 sin (N)

Where

(N) The time interval between the 1st and 3rd pulses of the clock, filled with N pulses. When measuring the amplitude of balance oscillations, it is usually set permissible values of the measured value P „„, and Ф „,,. that, according to the formula given, corresponds to a certain value of the impulses α „and (,„, i.e. max.

N - F

 min DSP. max, dop. The number N from the output of block 18 is compared in the digital comparator with the number Mmin. AOL and Mach. 40P, and the condition Mn, n, nn, N, c ,, c.Aon is fulfilled, the number N in the binary parallel code passes to the outputs of the digital comparator 19; if the condition is not met, voltage levels corresponding to level O are set at the outputs of the block.

Thus, digital comparator 19 performs the functions of a device confirming the fact that the measured parameter 9 i (N) is within a given range, increasing the reliability of the fact that the number N belongs to

lives to the region of changes in the values of the amplitude of balance oscillations.

The digital comparator 19 is made according to a standard scheme and contains a comparator and keys on logic circuits AND, on the run; which appears the number N in the binary parallel code or the level O when performing a comparison operation with settings.

The number N in the n-bit bottom of the binary parallel code from the outputs of the digital comparator 19 goes to the address inputs of the PISU block 20. Because there is a one-to-one relationship between the number N arriving at the address inputs of the PROM 20 and the corresponding value of the amplitude of balance oscillations pre-programmed, i.e., certain cells of the memory of the EPROM block 20, the binary code of the values of the amplitude of balance oscillations calculated by the given formula and the corresponding determined values of f, uniquely associated with the values and the numbers N. Therefore, the cell address is determined by the number N, and the readable result in the binary parallel code from the outputs of block 20 corresponds to the value of the amplitude of balance oscillations for a given number N. When the number M is set to the address inputs of block 50 and a negative pulse from the output of the first shaper 14 arrives at the read input of block 20, the amplitude of balance oscillations in the binary parallel code corresponding to a certain value of N appears at the output, i.e.

NF i- (N),

Where

N

T

amplitude value P represented in binary parallel code and functionally associated with the number N

The value of the measured amplitude of balance fluctuations in the h-bit bottom of the binary parallel code from the output of block 20 is fed to the information inputs of the display 21. Information on the measured value is recorded in the operational storage device (RAM) of block 21 upon the arrival of a delayed negative pulse from the output of the first shaper 14 pulses (through line 15 delay

to the input of the display 21. The pulse delay from the output of the first pulse shaper 14 is necessary so that the recording of information in the display 21 takes place with a certain time delay relative to the occurrence of N (p at the outputs of block 20, i.e. after the final setting the value of N at the outputs of block 20. The magnitude of the delay of the pulse arriving at the input of the display 21 relative to the pulse arriving at the input of the delay line 15 is determined by the parameters of the delay line 15. The delay line 15 is built on two AND-NOT logical elements on Received consecutively and provide a predetermined delay of the leading edge of the pulse entering the input of the delay line 15. The recorded value of the measured amplitude in the -ROM of the display 21 is displayed on the screen of the cathode-ray display of the display 21 in the form of decimal digits. type

Simultaneously with the arrival of a negative pulse from the output of the first driver 14 of the pulses to the input of the read resolution of block 20 and the input of the delay line 15, the blocks 6.9, 11 and 16 return to their initial state with the same pulse. After the termination of the negative pulse at the output of the first driver 14, the device is ready to carry out a new measurement of the amplitude of balance oscillations. The measurement of the second value of the amplitude of balance oscillations is similar to the first. The obtained amplitude value (second measurement) is again displayed on the screen of display 21, but already on the second line, etc. In this case, if the measured value of the balance oscillation amplitude falls outside the tolerance limits (the voltage levels corresponding to the level O are set at the inputs of block 19), the information Amplitude is not included in the tolerance on the corresponding line of the display 21. On each line of the display screen 21, a measurement number is also displayed, this is easily realized, since the number of measurements is equal to the number

pulses arriving at the input of the record display 21 ..

Claims (1)

Invention Formula A device for measuring the amplitude of oscillations of the balance of a mechanical clock, containing a sound signal sensor whose output is connected to an amplifier input, a pulse counter, a reference frequency source and a logic circuit AND, characterized in that, in order to improve the measurement accuracy, two comparators are detected in it, reference voltage source, saw-tooth voltage generator, front edge circuit, two pulse drivers, OR logic, standby multivibrator, delay lines and sequentially connected regs memory page, digital comparator, programmable read-only memory and display, the amplifier output being connected through a detector to the first input of the second comparator and the first input of the first comparator, the second input connected to the output of the reference voltage source, and the output to the first trigger input, the output of which is connected to the start input of the sawtooth generator and the first input of the logic circuit I, the second input connected to the output of the reference frequency source, and the output with the counting input, the counter pulses, the outputs of which are connected to the information inputs of the memory register, the output of the trigger through the sequentially switched-on multivibrator and the first pulse generator are connected to the input of the enable of the programmable memory storage, the input of the delay line, the reset trigger input, the inputs of the pulse counter, the circuits of the front and a sawtooth generator, the output of which is connected to the second input of the second comparator, is output through a serially connected circuit in isolating fronts, the second pulse generator and a logic OR circuit connected to the input of the memory write register at ztom output delay line connected to the display recording input. but and Uan and and and and and F and and and and- / V-1 I I Ш6 ffffom 11