SU1252919A1 - Multichannel measuring device for digital filtering - Google Patents

Abstract

The invention relates to computing and can be used in the construction of information-measuring systems and systems of automated control and management. The purpose of the invention is to distribute the functionality by performing averaging over any group of kaials. Delivered - the goal is achieved due to the fact that the device incorporates a clock pulse generator, an analog-digital converter, a frequency divider, a group of elements AND, a group of registers, a switch, a multiplier, accumulators, an adder, a multiplexer, a counter, a decoder, a three register, a fixed memory block, a comparison block, a memory block, and corresponding links between the blocks. 4 pe. g 1 (L Yu SL to O

Description

one

The invention relates to computing and can be used in the construction of information-measuring systems and systems for automated control and management.

The purpose of the invention is to expand the functionality by performing averaging over any group of channels,

FIG. 1 shows a functional diagram of the device; in fig. 2 - functional diagram of the analog-digital converter; on fkg, 3 - the scheme of the program block is functional; Fig. 4 is a functional block diagram.

The device (FIG. I) contains a clock pulse generator 1, an analog-to-digital converter 2, a divider 3 frequencies, a group of elements AND 4, a group of registers 5, a switch 6, a multiplier 7, a accumulator adder 8, a permanent memory block 9, a program block 10, a RAM 11, two registers 12 and 3j multiplexer 14 and a comparison block 15.

Analog-to-digital converter 2 (Fig. 2) contains normalization nodes 16, switch 17, decoder 18, voltage converter 19 — code, counter 20. Normalization nodes 16 are designed to convert various input signals to the same level. Program block 10 (FIG. 3) contains an address counter 21, a register 22 and a decoder 23, a comparison block 15 (FIG. 4) contains three combinational comparison nodes 24-26 and a decoder 27.

The device works as follows.

At the output of the divider 3 frequency synchronously with the pulses coming from the generator, there appears information through which, through the corresponding element 4, the code of the measured value of the input signal from the analog-to-digital converter of the electric actuator 2 writes into the corresponding register 5 each input signal (channel of the analog digital converter) corresponds to its register 5. Synchronously with the recording of information into registers 5, software block 10 operates, which synchronously with the generator 1 clock outputs the address to block 9 of the permanent memory. The information word issued by block 9 for each address of program block 10 contains the number of the input signal, which corresponds to the number of register 5, the multiplication factor (division) and the processing code (digital filtering) by which the digital filtering of the input signal occurs. Depending on this code the information from register 5 through switch 6 goes either to multiplier 7, where the measured value is multiplied by the corresponding weighting, the actions from the fixed memory block 9 through the software block 10 at multiplier 7, at this moment the information is filtered (processed in previous cycles) from memory block 1I goes to the input of adder 8, the second input of which receives information from multiplier 7, the output of adder 8 records the filtered value through multiplexer 14 either the RAM block or the information from register 5 through the switch 6 enters the input of the comparison block 15, to the other two inputs of which the information from the outputs of the registers 12 and 13 enters, where it goes from the RAM block 1 ty for two consecutive clock cycles of the generator 1, At the output; The comparison unit 15 contains the code of the average of the three values of the measured input signal. According to this code, the information from the corresponding registers 12 and 13 or the output of the 4th switch 6 through the multiplexer 14 is recorded in the operational memory unit 11.

The presence of registers 5 allows, regardless of the input signal measurements, to digitally process this signal. In order to store the first and second measurements (filtering code is the average value), the volume of the 1I block of the operative memory must be no less than twice the capacity of the registers 5, and The capacity of the fixed memory unit 9 is no less than three times the capacity of the registers 5 (which corresponds to the number of measurement signals e & 1x signals). Thus, for one input signal processed at the choice of the average value, in block 9 of the permanent memory three cells will be occupied. When reading the first cell of block 9, the program block

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10 writes information from register 5 through switch 6, multiplier 7, adder 8 and multiplexer 1 to the first area of the RAM 11 and to the first register t2; when reading the second cell of block 9, the program block in a similar way writes the measured value to the second area of the RAM block M and the second register 13; when reading the third cell of block 9, information from registers 2 and 13 and the switch 6 output goes to block 15 and The indicated average value of this information is, through multiplexer 14, written to memory unit 11. Since the address of the polled input signal and the filtering code are located, one information word of the persistent memory unit 9 (low-order is the number of the input signal or register 5, high-order is the filter code) the polling order of the memory cells can be selected. depending on the selected filtering and is determined only by the corresponding record in block 9 of the persistent memory.

Claims (1)

Invention Formula Multichannel measuring device for digital filtering, containing a clock pulse generator, the output of which is connected to the clock inputs of the frequency divider and an analogue-TsI) Ovogo converter, the output of which is connected to the first input of the i-ro (, M, M - number of channels) element And the group whose output is connected to the information input of the 1st register, the output of which is connected to the i-th information input of the switch, the output of which is connected to the first input of the multiplier, the output of which is connected 529194 to the first input of the accumulating sum- 1 mater, a block of permanent memory, the i-th output of the frequency divider is connected to The second input of an i-ro element AND group, 5 is characterized in that, in order to expand the functionality by performing averaging over any group of channels, three registers are entered into it, a multi-0 plexer, a memory unit, a comparison unit, a decoder and a counter The information output of which is connected to the address input of the block of permanent memory, the output of which is connected to the information 5 input of the first register, the output of which is connected to the input of the decoder, the outputs from the first to the sixth of which are connected respectively to the control input switch, control 2.0 input of the multiplexer, second input of the user, clock input of the second register, clock input of the rub register and control input of the memory unit whose output is connected to 25 information inputs of the second and third registers and the second input of the accumulating adder whose output is connected to the first information input of the multiplexer, the output of which is connected to the information input of the memory unit, the output of the second register is connected to the first input of the comparison unit and the second information input One multiplexer, the third J information input of which is combined with the second input of the comparator unit and connected to the output of the third register, the switch output is connected to the third input of the comparison unit, the output of which is connected to the fourth information input of the multiplexer, and the seventh decoder output to the installation counter input; account- N1Y} whose input is connected to the 5 OUTPUT of the clock pulse generator. i i YU 20 y 79 five w 77 79 T to L1H FIG 2 B K8L.9 - 21 Compiled A, Baranov Editor A. Kozoriz Tehred M. Khodanych Proofreader A, Tsko Order 4630/56 Circulation 816 Subscription VNIIPI USSR State Committee on inventions and opened} 113035, Moscow, Zh-35, Raushsk nab ,, d. 4/5 Production and printing company, Uzhgorod, st. Project, 4 YU t g ic OmSjr.3 Fig.Z