JP2009128130A - Voltage signal detector and abnormal voltage monitoring device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a voltage signal detector capable of shortening an execution time required for AD conversion, miniaturizing the whole, and monitoring for a long period an influence of an instantaneous noise having a small frequency of exerting an influence on output from a constant voltage power source. <P>SOLUTION: This voltage signal detector is equipped with a voltage measuring device for outputting a measurement signal 3 of a supply voltage; a plurality of comparators O1-O8 equipped respectively with a terminal for a voltage to be measured for applying a voltage to be measured which is not sample-held from the voltage measuring device and a reference voltage terminal for applying a reference voltage from a reference voltage generator 2, for comparing each voltage input respectively into the terminal for the voltage to be measured and the reference voltage terminal, and converting into a digital signal from the difference between both voltages, and for connecting each terminal in parallel; a voltage dividing circuit comprising a plurality of voltage dividing resistances R1-R8 connected between adjacent reference voltage terminals of each comparator O and between each power supply line of a comparator and the reference voltage generator on the terminal side, for dividing a reference voltage from the reference voltage generator; and a latch circuit 13 for latching output from each comparator O. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a voltage signal detector capable of detecting an abnormal voltage due to high-speed external noise in a DC constant voltage source or an AC constant voltage source, and an abnormal voltage monitoring device capable of monitoring the abnormal voltage.

  There are cases in which inductive noise or the like is externally applied to the constant voltage source output unit of the electronic device, and the electronic device malfunctions or stops. If this continues to be affected, it is possible to identify the affected area with a normal synchroscope or confirm that the countermeasure is good after taking the countermeasure.

  However, when the noise of the moment due to the operation of the external high-voltage contact is affected during the operation of the electronic device, the frequency of the noise exceeds 100 Mhz and the duration is as short as several hundred μS, and is generated There are cases where the frequency is less than once a year. In order to accurately observe such troubles, high-speed recording operation, long-term monitoring, and monitoring at many locations are necessary. However, the transient shown in the synchroscope and Non-Patent Document 1 described below is necessary. Memory devices have problems with high speed operation and size.

FIG. 7 is a block diagram showing a schematic configuration of the transient memory device shown in Non-Patent Document 1, in which an analog voltage measurement signal 3 from a constant voltage source (not shown) is converted by an AD converter 200 via a buffer 1, The converted digital data is stored in the storage device 205 under the control of the AD sequence controller 204. An external trigger signal or a manual stop signal causes the AD sequence controller 204 to stop writing to the storage device 205.
Here, as shown in Patent Document 1, the AD converter 200 includes an input buffer 201a, a sampling switch 201b, a sample hold unit 201 including a hold capacitor 201c, a parallel comparison type AD converter 202, and an encoder unit. 203.
Catalog of System Design Service Co., Ltd. (abbreviation: SDS) High-Speed Multi-Channel Transient Memory System Board “PC-G Series: High-Speed Multi-Channel Transient Memory System Board” (http://www.sds.co.jp/product/ adda / pci_board / index.html) JP 7-336225 A

This electronic device is usually intended to measure "waveform changes"
(1) Since the accuracy of the waveform is required, the AD converter 200 uses a high-accuracy one, and this cannot be performed at a high speed or a sufficiently high speed is very expensive. Even when the waveform accuracy is low, the operation speed is limited by the time required for the operation of the AD converter 200. Specifically, since the AD converter 200 includes the sample hold unit 201, the AD conversion unit 202, and the encoder unit 203, each of them requires time for processing.

  However, the original purpose of the above-described electronic device is to detect a trouble and identify that the cause is instantaneous noise that affects the power supply, and the detected voltage waveform does not need to be highly accurate.

(2) Since the above-described electronic device is intended to observe a change in waveform, the above-described storage device 205 has a large capacity and a large size, and is used to monitor infrequent instantaneous noise over a long period of time. Therefore, there is a demand for a small abnormal voltage monitoring device that can be arranged even in a gap between adjacent devices.

  The present invention has been made to overcome the above-mentioned problems. The execution time required for AD conversion can be shortened, the entire size can be reduced, and the influence of instantaneous noise, which has a low frequency affecting the output of the constant voltage power supply, can be reduced for a long time. An object is to obtain a voltage signal detector and an abnormal voltage monitoring device that can be monitored.

  In order to achieve the above object, the invention corresponding to claim 1 includes a voltage measuring device for measuring a power supply voltage, a reference voltage generator for generating a reference voltage, and each of which is not sample-held from the voltage measuring device. A voltage terminal to be measured for applying a voltage to be measured and a reference voltage terminal to which a reference voltage from the reference voltage generator is applied, and comparing the voltages inputted to the voltage to be measured terminal and the reference voltage terminal, respectively. A plurality of comparators connected in parallel to each other, a comparator between adjacent reference voltage terminals of each of the comparators, and a power supply line of the reference voltage generator A voltage dividing circuit comprising a plurality of voltage dividing resistors connected in between and dividing a reference voltage from the reference voltage generator, and a latch circuit for latching outputs of the plurality of comparators synchronously, in front A voltage signal detector, characterized in that to be able to detect a change in waveform of the measured voltage from the voltage measuring device.

 In order to achieve the above object, the invention corresponding to claim 2 is directed to a voltage measuring device for measuring a power supply voltage, a reference voltage generator for generating a reference voltage, and applying a measured voltage from the voltage measuring device to each. A voltage terminal to be measured and a reference voltage terminal for applying a reference voltage from the reference voltage generator, compare voltages input to the voltage terminal to be measured and the reference voltage terminal, respectively, and convert the difference between the two to a digital signal. A plurality of comparators that are connected in parallel, a comparator for detecting abnormal voltage between adjacent reference voltage terminals of each of the comparators and a terminal side, and a power supply line of the reference voltage generator A voltage dividing circuit comprising a plurality of voltage dividing resistors connected in between and dividing a reference voltage from the reference voltage generator; a latch circuit for latching outputs of the plurality of comparators synchronously; and a clock at a predetermined cycle Signal A clock signal generator for providing a latch instruction signal to the latch circuit by the clock signal, a latch instruction signal for latching an output of the comparator by a clock signal from the clock signal generator, and An abnormal voltage monitoring device comprising: a writing circuit for writing data of the comparator latched by the latch circuit to a recording device.

 In order to achieve the above object, the invention corresponding to claim 3 is a voltage measuring device for measuring a power supply voltage, a reference voltage generator for generating a reference voltage, and applying a voltage to be measured from the voltage measuring device to each. A voltage terminal to be measured and a reference voltage terminal for applying a reference voltage from the reference voltage generator, compare voltages input to the voltage terminal to be measured and the reference voltage terminal, respectively, and convert the difference between the two to a digital signal. A plurality of comparators that are connected in parallel, a comparator for detecting abnormal voltage between adjacent reference voltage terminals of each of the comparators and a terminal side, and a power supply line of the reference voltage generator A voltage dividing circuit composed of a plurality of voltage dividing resistors connected to each other to divide a reference voltage from the reference voltage generator, a latch circuit that latches outputs of the plurality of comparators synchronously, and a clock at a predetermined cycle Signal A clock signal generator for providing a latch instruction signal to the latch circuit in response to the clock signal, and a latch instruction signal for incrementing the clock signal from the clock signal generator and latching the output of the comparator And an address generation circuit for generating an address when the data of the comparator latched by the latch circuit is written to a recording device.

 In order to achieve the above object, the invention corresponding to claim 4 includes a voltage measuring device for measuring a power supply voltage, a reference voltage generator for generating a reference voltage, and a voltage to be measured from the voltage measuring device applied to each. A voltage terminal to be measured and a reference voltage terminal for applying a reference voltage from the reference voltage generator, compare voltages input to the voltage terminal to be measured and the reference voltage terminal, respectively, and convert the difference between the two to a digital signal. A plurality of comparators connected in parallel with each other, connected between adjacent reference voltage terminals of each of the comparators and between a comparator on the terminal side and a power supply line of the reference voltage generator; A voltage dividing circuit composed of a plurality of voltage dividing resistors for dividing a reference voltage from the reference voltage generator; a latch circuit for latching outputs of the plurality of comparators in synchronization; and a clock signal at a predetermined cycle; This black A clock signal generator for providing a latch instruction signal to the latch circuit by a clock signal, a latch circuit for incrementing a clock signal from the clock signal generator and latching an output of the comparator, and the latch An address generation circuit for generating an address when writing the data of the comparator latched in the circuit to a recording device; and the abnormality detection signal regarded as abnormal among the outputs of the comparator for a predetermined time after the output An abnormal voltage monitoring device comprising a timer for validating a signal for writing data of a comparator to a recording device.

 In order to achieve the object, the invention corresponding to claim 5 is as follows. That is, the abnormal voltage monitoring device according to any one of claims 2 to 4, wherein writing to the recording device cannot be performed when there is a signal indicating a data read state from the recording device. It is.

  The present invention provides a voltage signal detector and an abnormal voltage monitoring device that can shorten the execution time required for AD conversion, reduce the overall size, and monitor the influence of instantaneous noise that has a low frequency affecting the output of a constant voltage power source for a long period of time. it can.

  Hereinafter, embodiments of a voltage signal detector and an abnormal voltage monitoring device of the present invention will be described with reference to the drawings.

[Embodiment 1]
FIG. 1 is a block diagram of Embodiment 1 of the voltage signal detector and the abnormal voltage monitoring apparatus of the present invention.

(Constitution)
First, a voltage signal detector according to a first embodiment of the present invention will be described with reference to FIG. A voltage measuring device (not shown) that measures a voltage of a constant voltage power source (not shown) and outputs a measurement signal 3; a reference voltage generator (reference voltage setting device) 2 that generates a reference voltage; The voltage to be measured is applied to the measured voltage terminal and the reference voltage terminal, respectively, with a measured voltage terminal for applying the measured voltage not sampled and held from the reference voltage terminal for applying the reference voltage from the reference voltage generator 2 Are compared to each other and converted into a digital signal, and a plurality (eight in this case) of comparators O1, O2, O3, O4, O5, O6, O7, O8, which are connected in parallel, References from the reference voltage generator 2 are connected between adjacent reference voltage terminals of the comparators O1 to O8 (hereinafter simply referred to as O) and between the comparator O8 on the terminal side and the power supply line of the reference voltage generator 2. A voltage divider The voltage dividing circuit composed of (here, 8) voltage dividing resistors R1, R2, R3, R4, R5, R6, R7, R8 (hereinafter referred to as each voltage dividing resistor R) and the output of each comparator O are synchronized. And a latch circuit 13 for latching, and a comparator protection resistor R0 connected between the measured voltage terminal of the comparator O8 and the ground terminal.

  Each voltage dividing resistor R and each comparator O does not include a sample hold unit, and constitutes an AD conversion circuit 11 using, for example, a discrete circuit. The voltage signal detector having such a configuration can detect a change in the waveform of the voltage to be measured from the voltage measuring device.

(Function)
Next, the effect | action in Embodiment 1 is demonstrated. The AD conversion circuit 11 divides the reference voltage from the reference voltage setter 2 by a plurality of resistors R, and the reference voltage signal for comparison of each comparator O obtained by dividing the reference voltage by the plurality of resistors R and the signal under measurement 3 by each comparator O. The signal under measurement 3 is digitized by comparison. On the other hand, the high-speed clock generated by the clock generator 12 itself generates a latch instruction signal for the digitized signal latch circuit 13 and latches the digitized signal.

(Action / Effect)
FIG. 2 is a diagram for explaining the operational effect of the AD converter circuit 11, that is, the merit of not including the sample hold unit. FIG. 2A is a voltage measurement signal (measurement input voltage) 3 of a constant-voltage power supply device (not shown). (B) and (c) are diagrams showing examples of outputs from the respective comparators O. In (a), d is an example when the voltage measurement signal 3 falls from a high state, and this value d is directly output to the measured voltage terminal of each comparator O. The output of each comparator O is A digital value as shown in (b) is latched in the data latch circuit 13 which latches synchronously. As a result, the performance of each comparator O may vary depending on the change in the voltage measurement signal 3 due to variations in performance.

 In (a), u is an example when the voltage measurement signal 3 rises from a low state, and this value u is directly output to the measured voltage terminal of each comparator O. In the data latch circuit 13 that latches in synchronization with each other, a digital value as shown in (c) is latched. As a result, the performance of each comparator O may vary depending on the change in the voltage measurement signal 3 due to variations in performance. Thus, by allowing the variation in accuracy of the AD converter circuit 11 to the extent described above, the sampling time of the normal AD converter circuit and the time of the decoder can be saved. This is an advantage because the sample hold unit 201 is not provided.

  FIG. 3 is a diagram for explaining speeding up, which is a merit of the first embodiment. The solid line in FIG. 3 shows the voltage measurement signal 3. When the voltage measurement signal 3 changes as shown in FIG. 3, the bit is surely “1”, depending on the characteristics of each comparator O as shown by Δ. There are so-called indefinite bits that are not defined as "1" or "0". For example, the most significant bit indicating “1” is adopted as the voltage value, or the processing for considering only the signal having “1” continuous from the least significant bit as significant is provided in the subsequent stage of the storage device. The accuracy is sufficiently satisfied and high speed can be realized.

  According to the voltage signal detector described above, the execution time required for AD conversion can be shortened, and the entire size can be reduced. Further, since the AD conversion circuit 11 does not include the sample hold unit 201 and the encoder unit 203 shown in FIG. 7, the circuit is simple and the accuracy is low, but the circuit unit is simple and high-speed conversion is possible. . In the embodiment, the voltage is divided into 8 and the memory is assumed to be an 8-bit memory. However, the voltage is divided into 16 or more, and the memory is provided with a 16-bit correspondence and a separate memory bank to increase the accuracy. May be realized.

 In FIG. 1, a clock generator 12, a shaping circuit 10, a recording device such as a memory 14 and a writing circuit 15 are provided, and all of them constitute an abnormal voltage monitoring device.

According to this abnormal voltage monitoring apparatus, since the voltage signal detector described above is provided, the signals latched in synchronism with the data latch circuit 13 are respectively written into the memory 14 by the memory write circuit unit 15 at the subsequent stage. . As a result, it is possible to monitor for a long time the influence of instantaneous noise that has a low frequency affecting the output of the constant voltage power supply.

  In addition, a battery-driven small and high-speed monitoring device can be realized. Furthermore, by arranging this small monitoring device not only on one electronic device but also on a large number of electronic devices, it becomes possible to monitor and measure the entire electrical environment at the installation location.

[Embodiment 2]
(Constitution)
The second embodiment will be described with reference to FIG. 1 is different from FIG. 1 in that an address generation circuit unit including an increment counter 21 that inputs a clock signal from the clock generator 12 and gives an address to the memory 14 is added. Therefore, the same parts are denoted by the same reference numerals and description thereof is omitted.

(Function)
The address when the digitized signal latched in the first embodiment is written to the memory 14 is performed by the address generation circuit unit by the increment counter 21. This mechanism is a signal obtained by simply incrementing the clock signal from the clock generator 12 used for the data latch. A clock signal from the clock generator 12 is shaped by the shaping circuit 9 to create a write signal for writing to the memory 14.

(effect)
According to the second embodiment, since the address generator is configured with a simple increment counter 21 and writing to the memory 14 can be performed immediately after the data latch, the writing speed can be increased. In this case, the bit length of the clock counter can be limited to the size determined by the generated address, and the memory usage can be reduced.

  In this example, writing to the memory 14 is performed in a single-stage memory bank configured in series from the AD conversion circuit 11. However, in order to improve the memory writing speed, a plurality of AD conversion data latch circuits 13 and the following are arranged in parallel. It may be performed in parallel while distinguishing which latch circuit data is written to which bank.

[Embodiment 3]
(Constitution)
Although Embodiment 3 will be described with reference to FIG. 5, the same parts as those in FIGS. 1 and 4 are denoted by the same reference numerals, and description thereof will be omitted. The comparator O8, which is the output of the comparator O8 at the end of the voltage dividing circuit in the comparator O, takes in the detection signal of the lowest abnormal voltage and records the data of the comparator O8 only for a certain time after the detection of the abnormal voltage detection signal. For example, the difference is that an off-delay timer 31 for enabling a signal to be written in the memory 14 is provided. The same parts other than that are denoted by the same reference numerals and description thereof is omitted.

(Function)
According to the third embodiment, the output of the comparator O8 at the bottom of the AD converter circuit 11 is regarded as an abnormal voltage detection signal, and after this signal is turned on, the write signal to the memory 14 for a certain period of time by the off-delay timer 31. Becomes effective.

(effect)
According to the third embodiment, writing to the memory 14 can be further limited as compared with the second embodiment.

  The third embodiment described above may be modified as follows. That is, the operation of the off-delay timer 31 is not limited to the output of O8 among the outputs of the comparator O, but is an abnormality detection signal that regards the outputs of the other comparators O1, O2, O3, O4, O5, O6, and O7 as abnormal. The signal for writing the data of the comparator to the recording device, for example, the memory 14 may be validated for a certain period of time after the signal is output.

[Embodiment 4]
(Constitution)
Embodiment 4 of the present invention will be described with reference to FIG. 6, but the same parts as those in FIGS. Writing to the recording device, for example, the memory 14 is not performed when there is a signal (reading signal) 41 indicating a data reading state from a data reading circuit unit (not shown). Therefore, a logical product having one inverting input terminal between the data latch circuit 13, the off-delay timer 31 and the increment counter 21, the off-delay timer 31 and the memory 14, and the data line during data reading. Circuits 7, 6 and 8 are provided, respectively.

  This configuration may be applied to any one of Embodiments 1, 2, and 3 described above.

(Action))
While a data reading circuit unit (not shown) is operating, a data reading signal 41
Therefore, the counter 21, the data latch circuit 13, and the data writing are not valid.

(effect)
According to the fourth embodiment, since it is not necessary to operate during data reading, the circuit is simplified and the speed can be increased.

[Modification]
The comparator O used in the above-described embodiment may be either an operational amplifier or a comparator.

  In the above-described embodiment, the abnormal signal is extracted from the output (minimum value) of the comparator O8 on the terminal side. However, the present invention is not limited to this, and other comparators O1, O2, O3, O4, O5, O6, The output may be O7.

The block diagram for demonstrating Embodiment 1 of the voltage signal detector and abnormal voltage monitoring apparatus of this invention. The figure for demonstrating the effect of FIG. The figure for demonstrating the effect of FIG. The block diagram for demonstrating Embodiment 2 of the abnormal voltage monitoring apparatus of this invention. The block diagram for demonstrating Embodiment 3 of the abnormal voltage monitoring apparatus of this invention. The block diagram for demonstrating Embodiment 4 of the abnormal voltage monitoring apparatus of this invention. The block diagram which shows schematic structure of the conventional abnormal voltage monitoring apparatus.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Buffer, 2 ... Reference voltage generator, 6, 7, 8 ... AND circuit, 9 ... Shaping circuit, 10 ... Shaping circuit, 11 ... AD converter circuit, 12 ... Clock generator, 13 ... Data latch circuit, 14 ... Memory, 15 ... Write circuit, 21 ... Increment counter, 31 ... Off-delay timer, 200 ... AD converter, 201a ... Input buffer, 201b ... Sampling switch, 201c ... Hold capacitor, 201 ... Sample hold unit, 202 ... AD conversion Reference numeral 203, an encoder unit, 204, an AD sequence controller, 205, a storage device.

Claims (5)

A voltage measuring instrument for measuring the power supply voltage;
A reference voltage generator for generating a reference voltage;
A voltage terminal to be measured for applying a voltage to be measured, which is not sample-held from the voltage measuring instrument, and a reference voltage terminal for applying a reference voltage from the reference voltage generator, and the voltage terminal to be measured and the reference voltage Comparing the voltage input to each terminal and converting the difference between the two into a digital signal, a plurality of comparators connected in parallel,
Connected between adjacent reference voltage terminals of each of the comparators and between the comparator on the terminal side and the power supply line of the reference voltage generator, and from a plurality of voltage dividing resistors for dividing the reference voltage from the reference voltage generator A voltage divider circuit,
A latch circuit for synchronizing and latching outputs of the plurality of comparators;
And a voltage signal detector characterized in that a change in the waveform of the voltage to be measured from the voltage measuring device can be detected. A voltage measuring instrument for measuring the power supply voltage;
A reference voltage generator for generating a reference voltage;
Each has a measured voltage terminal for applying a measured voltage from the voltage measuring instrument and a reference voltage terminal for applying a reference voltage from the reference voltage generator, and is inputted to the measured voltage terminal and the reference voltage terminal, respectively. A plurality of comparators, each of which is connected in parallel,
A plurality of differential voltage detectors connected between adjacent reference voltage terminals of each of the comparators and between a comparator for detecting abnormal voltage on the terminal side and a power supply line of the reference voltage generator, and for dividing the reference voltage from the reference voltage generator. A voltage dividing circuit comprising a voltage dividing resistor of
A latch circuit for latching outputs of the plurality of comparators synchronously;
A clock signal generator that generates a clock signal at a predetermined period and provides a latch instruction signal to the latch circuit by the clock signal;
A latch instruction signal for latching an output of the comparator by a clock signal from the clock signal generator; and
A writing circuit for writing the data of the comparator latched by the latch circuit to a recording device;
An abnormal voltage monitoring device comprising: A voltage measuring instrument for measuring the power supply voltage;
A reference voltage generator for generating a reference voltage;
Each has a measured voltage terminal for applying a measured voltage from the voltage measuring instrument and a reference voltage terminal for applying a reference voltage from the reference voltage generator, and is inputted to the measured voltage terminal and the reference voltage terminal, respectively. A plurality of comparators, each of which is connected in parallel,
A plurality of differential voltage detectors connected between adjacent reference voltage terminals of each of the comparators and between a comparator for detecting abnormal voltage on the terminal side and a power supply line of the reference voltage generator, and for dividing the reference voltage from the reference voltage generator. A voltage dividing circuit comprising a voltage dividing resistor of
A latch circuit for latching outputs of the plurality of comparators synchronously;
A clock signal generator that generates a clock signal at a predetermined period and provides a latch instruction signal to the latch circuit by the clock signal;
A latch instruction signal for incrementing the clock signal from the clock signal generator and latching the output of the comparator; and a latch circuit;
An address generation circuit for generating an address when writing the data of the comparator latched by the latch circuit to a recording device;
An abnormal voltage monitoring device comprising: A voltage measuring instrument for measuring the power supply voltage;
A reference voltage generator for generating a reference voltage;
Each has a measured voltage terminal for applying a measured voltage from the voltage measuring instrument and a reference voltage terminal for applying a reference voltage from the reference voltage generator, and is inputted to the measured voltage terminal and the reference voltage terminal, respectively. A plurality of comparators, each of which is connected in parallel,
Connected between adjacent reference voltage terminals of each of the comparators and between the comparator on the terminal side and the power supply line of the reference voltage generator, and from a plurality of voltage dividing resistors for dividing the reference voltage from the reference voltage generator A voltage divider circuit,
A latch circuit for latching outputs of the plurality of comparators synchronously;
A clock signal generator that generates a clock signal at a predetermined period and provides a latch instruction signal to the latch circuit by the clock signal;
A latch instruction signal for incrementing the clock signal from the clock signal generator and latching the output of the comparator; and a latch circuit;
An address generation circuit for generating an address when writing the data of the comparator latched by the latch circuit to a recording device;
A timer for validating a signal for writing the data of the comparator to the recording device for a certain period of time after an abnormality detection signal regarded as abnormal among the outputs of the comparator is output;
An abnormal voltage monitoring device comprising:   The abnormal voltage monitoring device according to claim 2, wherein writing to the recording device is disabled when there is a signal indicating a data reading state from the recording device.

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