SU1251107A1 - Digital correlator - Google Patents

Abstract

The invention relates to the field of sophisticated technology and can be used in automatic control and monitoring systems, as well as in digital signal processing devices. The purpose of the invention is to increase the speed of the correlator, which is achieved by calculating the correlation estimates without performing the multiplication operation in an explicit form. The digital correlator contains two analog-digital converters, four registers, two memory blocks, an EXCLUSIVE OR element, an adder, a comparator, a switch, a clock generator, an AND element, and a synchronization unit. The comparator and the switch select and transmit a smaller modulo code value to the fourth register, and a larger one to the third register. The introduction of the EXCLUSIVE OR element with appropriate functional links allows one to go from cyclic execution of the multiplication operation to its execution in one operation of comparison of codes and several shift operations and thereby obtain a significant gain in the speed of calculating the values of correlation functions. 2 Il. i (L

Description

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The invention approaches computers and can be used in automatic control and monitoring systems, for example, in radiolocation.

The aim of the invention is to increase the speed of the correlator.

Figure 1 shows the structural diagram of Gerelle Torau in figure 2 - the block diagram of the synchronization block umi.

The correlator (figure 1 / contains the first analog-to-digital converter 1, the first register 2, the first memory block 3, the second register 4, the second analog-digital converter 5, the EXCLUSIVE OR element 6 comparator 7 switch 8, the third register 9 , fourth register 10, clock generator 11, cz mmator 12, second memory block 13, AND element 14, synchronization unit 5, first input 16 of the correlator, second input 7 of the correlator, output 18 of the correlator.

The synchronization unit 15 of the correlator (figure 2) contains a single pulse generator 19, the first delay element 20, the first element OR 21, the first trigger 22, the first element AND 23, the first element OR 24, the second delay element 25, the third element ШШ 26 , the third delay element 27, the fourth element OR 28, the fourth and fifth elements 29 and 30 of the delay, the second element AND 31, the first master oscillator 32, the fifth and sixth elements OR 33 and 34, the second trigger 35 the third element AND 36, the seventh the element OR 37, the sixth and seventh elements 38 and 3 of the delay, the fourth element And 40, the eighth and the eighth elements OR 41 and 42, the third trigger 43, the fifth element And 44, the eighth and ninth elements 45 and 46 of the delay, the second down generator 47, the element RSHI 48, the fourth trigger 49, the sixth element And 50, the tenth and eleventh elements 51 and 52, the tenth, eleventh, and twelfth elements of ШП 53-55, twelve

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R.y (ut) m

sign y, 9 m

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the thirteenth and thirteenth elements 56 and 57 of the delay, the counters 58 and 59 of the address and works, fourteen, fifth, sixteenth and seventeenth delay elements 60-63, the seventh element AND 64, the first, the third, the fourth, the fifth, the sixth, the seventh, nine, ten, my, eleventh, thirteenth, twelfth, and second exits are 66, 67, 70, 69,71,77,72,73,68,74,65,76 and 75, respectively.

The digital correlator works as follows.

The inputs 16 and 17 receive signals x (t) and y (t) respectively. Passing through analog-to-digital converters 1 and 5, their digitized modular values, represented in natural form, after being stored on the corresponding registers 2, 4 and delays in the first memory block 3 are fed to the inputs of the comparator 7 and switch 8. They provide transferring a smaller digital code to the third register 9, and a larger one to the fourth register 10. This distribution of digital codes over registers 9 and 10 actually provides a relay method for determining the correlation function, since in the future all computational operations are performed on only one, smaller in modulus, digital code located in the third register 9. In addition, the higher bit of the modular value of a larger digital code is analyzed in the correlator to obtain a smaller digital code in order to obtain higher accuracy of intermediate products. The modular values of the works thus obtained are fed to the input of the sugator 12, to the sign input of which, from the output of the element EXCLUSIVE OR 6, receives the sign of the product. At adder 12, together with the second memory block 13, a final evaluation of the correlation function is formed:

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at) x,., /;

  2, with / x J.

31

where Ktx (K |) is the number of zeros (the number of shifts) between the comma and the first significant digit of the input code X. c, (Y;)),

To organize the synchronous operation of individual blocks and calculate the correlation function estimate in a parallel-sequential way. according to the expression. (1) Synchronization unit 15 is used. The operation of the digital correlator is synchronized by four sequences of pulses generated by block 15. Operation of block 15 begins with the generation of a single pulse of control signal 65 RESET by the generator. This control signal provides for setting to the initial zero state of the block 13, the first 22, the second 35, the third 43 and the fourth 49 triggers, as well as the counters 58 of the address and 59 products. Delayed in the first delay element 20, the control signal RESET sets the first trigger 22 to one state, allowing the transmission of clock pulses generated by the first master oscillator 32 through the first 23 And to the input of the second delay elements 27. As a result, the first sequence of control signals is generated with a clock frequency of the first master oscillator 32:

T-1 START ADC - control signal 66, which ensures the formation and output of digitized values from the outputs of the first and second analog digital converters 1 and 5, as well as transferring the first 2 and second 4 registers to the zero state, with the last prepared for: receiving new information from the first I and second 5 analog-to-digital converters;

1-2 WRITING IN REGISTERS 1 and 2 C ADC control signal 67;

T-W RECORDING IN BLOCK 3 is a control signal 69, providing para-phase recording of information from the output of the first register 2 into the memory cell of block 3 at the current address generated by the address counter 58.

As a result, after generating the t-1 times the first sequence of control signals, the unit is 15 seconds.

YOU, the frequency of the second generator 47 generates a second sequence of control signals:

I-1 START ADC - control signal 66;

II-2 RECORDING IN REGISTERS 1 AND 2 WITH ADC - sending signal 67;

II-3 RECORDING IN BLOCK 3 - control signal 69;

II-4 RECORDING TO REGISTERS 9 and 10 - control signal 72, which provides paraphase recording of information in registers 9 and 10, coming from the output of switch 8, controlled by comparator 7;

11-5 START OF THE GENERATOR - control signal 73, which ensures the start of the generator 11;

II-6 READING FROM BLOCK 13 - control signal 74, providing paraphase reading of information into adder 12 from block 13 at the current address generated by address counter 58;

II-7 ELEPHANT {ENZH - control signal 75, which provides for the addition of the addition operation in the adder 12;

II-8 RECORDING INTO BLOCK 13 - control signal 76, which provides para-phase recording of information from the adder 1 2 to block 13 at the current address generated by the address counter 58

III-1 READING FROM BLOCK 3 - control signal 71, which provides paraphase reading of information in the first register 2 from block 3 to the current address; formed by the counter 58 addresses;

III-2 WRITING IN REGISTER 2 - control signal 70, providing a paraphase recording of information from block 3 to the first register 2;

III-8 REGENERATION - control signal 77, which provides regeneration (rewriting information from the i-th cell into (1-1) -th memory cell) of information in block 3. At the same time, this control signal translates the third trigger 43 into one the first state (this allows the generation of the second sequence of control signals), the fourth trigger 49 to zero (the generation of the third sequence of control signals ceases), and also enters the input of the counter 59

works to form the next (larger by unit lower-order) number of the current work.

The generation of the second and third control signal sequences is terminated by an overflow signal generated by a counter 59 of works. The overflow signal transfers the fourth trigger 49 to the zero state, and the second trigger 35 to the single state. As a result, after generating N-ra times the second sequence of control signals and (Nm) (ml) times the third sequence of control signals, the block 53 s the clock frequency of the first master oscillator 32 generates the fourth sequence of control signals s

IV-J READING FROM BLOCK 13 - control signal 74, which provides paraphase reading of information on the display device from block 13 to the current address generated by address counter 58. This control signal through the seventh delay element 39 is fed to the input of the address counter 58 to form the next (greater by one least significant bit) number of the current readout address. Simultaneous control signal 74 through the sixth delay element 38 is fed to the fourth element. And 40. The latter, taking into account the contents of the counter 58 of the address, generates a transfer signal to. the zero state of the second flip-flop 35, the control signal 68 of the block 15 is the L-bit code of the address received at the inputs of the blocks 3 and 13.

At this point, the operation of the digital correlator ceases.

The outputs of the control signals I-, 1-2 and 1-3 and IT.-3 are common to the individual digital correlator nodes, and the input logic elements OR 24, 26, 28 and 37 respectively are combined . Logic elements And 3L 40 and 64 are multi-input with the number of inputs L + 1, where L is the bit size of the binary counter 58 address., And represent the elements of the incomplete decoder.

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15 20

25 so

55

45

50

Formula and 3 onbretam

The digital correlator containing the first and second analog-to-digital converters, the first, second, third and fourth registers, the first and second memory blocks, the comparator, the switch, the And element, the adder, the synchronization unit and the clock generator, the information inputs of the first and the second analog-digital converters are the first and second bi-Ns information inputs of the correlator, respectively, the outputs of the first and second analog-digital converters are connected to the information inputs rtepBoro and the second registers with Respectively, the bit outputs of which are connected to the corresponding information inputs of the switch, the combined start inputs of the first and second analog-to-digital converters are connected to the first output of the synchronization unit, the resolution input sum 1 1 day of the gmator is connected to the second output of the synchronization unit, characterized in that , in order to increase the speed, an EXCLUSIVE OR element is introduced into it, the third output of the synchronization unit is connected to the combined inputs of the recording resolution of the first and second registers, The joint zeroing inputs of which are connected to the first output of the synchronization unit, the fourth output of which is connected to the additional recording enable input of the first register, the fifth output of the synchronization unit is connected to the first recording enable input of the first memory block, the input of which is connected to the sixth output of the synchronization unit , the seventh output of which is connected to the second input of the recording resolution of the first memory block, the address inputs of the first and second memory blocks are combined and connected to the eighth output of the block with Synchronization, the ninth output of which is connected to the combined enable inputs of the third and fourth registers, the tenth output of the synchronization unit is connected to the trigger input of the clock generator, the eleventh output of the synchronization unit is connected to the read input of the second memory unit, the first write enable input of which is connected with the twelfth exit71

the synchronization block house, thirteenBT whose output is connected to the second recording enable input of the second memory block, the information input-output of the first register is connected to the information input-output of the first memory block, the bit outputs of the first and second registers are connected to the corresponding information inputs the comparator, which outputs are Larger and Less than which are connected to the corresponding control inputs of the switch, the first and second information outputs of which are connected to the information inputs of the third and fourth th registers, respectively, whose clock inputs obedi1078

and the first input of the element I is connected to the output of the clock generator, the output of the third register is connected to the first information input of the amp1-1mator, the second information input of which is connected to the output of the element EXCLUSIVE OR, the first and second inlets, the formation inputs of which are connected to the sign outputs of the first and second registers, respectively, the informational input-output of the adder is connected to the information input-output t The first memory block whose output is the output of the correl tor1.

Editor I.Rybchenko

Compiled by E.Efimova Tehred M.Hodanich

Order 4413/47 Circulation 67 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, Projecto st., 4

Proofreader A. Obruchar

Claims (1)

Claim A digital correlator containing the first and second analog-to-digital LRE5 educators, the first, second, third and fourth registers, the first and second memory blocks, a comparator, a switch, an And element, an adder, a synchronization unit and a clock generator, the information inputs of the first and second analog-to-digital converters are the first and second information inputs of the correlator, respectively, the outputs of the first and second analog-to-digital converters are connected to the information inputs of the first and second registers Accordingly, the bit outputs of which are connected to the corresponding information inputs of the switch, the combined triggering inputs of the first and second analog-to-digital converters are connected to the first output of the synchronization unit, the adder totalization enable input is connected to the second output of the synchronization unit, which is characterized by the fact that, in order to improve performance , an EXCLUSIVE OR element is inserted into it, the third output of the synchronization block is connected to the combined “write” inputs for recording the first and second registers, combined the null input inputs of which are connected to the first output of the synchronization unit, the fourth output of which is connected to an additional input enable recording of the first register, the fifth output of the synchronization unit is connected to the first input of the write enable of the first memory unit, the read input of which is connected to the sixth output of the synchronization unit, the seventh output of which connected to the second recording permission input of the first memory block, the address inputs of the first and second memory blocks are combined and connected to the eighth output of the synchronization block, the ninth output of which is connected to the combined recording permission inputs of the third and fourth registers: the tenth output of the synchronization block is connected to the trigger input of the clock generator, the eleventh output of the synchronization block is connected to the read input of the second memory block, the first recording permission of which is connected to the twelfth output synchronization, the thirteenth output of which is connected to the second input of the recording permission of the second memory block, the information input-output of the first register is connected to inform - j by the input-output of the first memory block, the bit outputs of the first and second registers are connected to the corresponding information inputs of the comparator, the Volde and 10 outputs are less than which are connected to the corresponding control inputs of the switch, the first and second information outputs of which are connected to the information inputs of the third and fourth registers accordingly, the synchronization inputs of which are connected and connected to the output of the element And, the first input of which is connected to the output of the fourth register, the second input is ment And is connected to the output of the clock generator, the output of the third register is connected to the first information input of the adder, the second information input of which is connected to the output of the EXCLUSIVE OR element, the first and second information inputs of which are connected to the sign outputs of the first and second registers, respectively, the information input - the output of the adder is connected to the information input-output of the second memory block, the output of which is the output of the correlator. fie. 1 fie. 2