SU1249563A1 - Device for reception of digital information - Google Patents

Abstract

The invention relates to digital information exchange systems and is intended for use in a multi-subscriber system: communications. The difference between the proposed device and the known ones is that it allows one to receive both uncompressed and compressed information represented in serial code and convert it into parallel code. In order to extend the functionality, two key blocks and a code converter are inserted into the device, allowing, depending on the value of the control signal, to receive one or the other type of information and decode the compressed information. 2 hp f-ly, 1 ill. (Ls

Description

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The invention relates to digital information exchange systems and is intended for use in multi-component communication systems.

The purpose of the invention is to expand the range of application of the device due to the use of both uncompressed and compressed digital information.

The drawing shows the functional scheme of the device.

The device contains a receiver 1 of a sequential code, which includes the element And 2, block 3 and differentiation and divider 4 ,, the device also contains the first and second elements And 5 and 6, the element NOT 7, the splitter 8, the first register 9 the first and second blocks 10 and 11 keys, the second register 12e is the converter of the 13th code, which includes the block of 14 elements of the DRAWING ORDER, consisting of the elements 14.1-14,7 CONCLUSIVE OR, the register 15., the driver 16 of the signal, the decoder 17, the element AND 18, item NOT 19 and counter 20,

The device operates in a multi-subscriber communication system. In this system, information over the communication channel is normally transmitted by a two-frequency signal receiving two levels, where the code unit is transmitted by switching in the middle of the symbol transfer cycle from the upper level to the lower level, and code zero is switched from the lower level to the upper level. When transmitting sequences of ones or zeros, an additional signal switching from one level to another is performed at the boundary of the contact. Thus, each code symbol is transmitted in two half-cycles.

When the system is operating in the mode of information transmission with compression in a communication line, a signal with the same characteristics as in the normal mode is used, the compression of the same information is achieved by recoding it.

The signal from the communication line is fed to the input of receive circuit 1, to the second input of which a pulse clock signal is received, whose frequency is several times (for example, 8 times) higher than the frequency of received information half-cycles. The code entering receiver 1 gets to the second one, the input of element 2, and passes through differentiation unit 3, where for each switch

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of the input signal, a pulse is generated that arrives at the first input () of the initial setup) divider 4 Divider 4, made in the considered variant in the form of a three-bit d-Hoi o binary counter, divides the frequency of the input clock signal to the value equal to the frequency of information half-cycles. Under the action of the signal with vytO, the trimmer stroke, due to the initial setting of the counter state at the output of the divider 4, clock signals are generated at times corresponding to the midpoint of the half-clock received

15 information. As a result, at the output of element 2, a signal appears only in those half-steps of the received information signal, when it has a high level. Output signals

The 20 elements And 2 and divider 4 are fed to the output of receiver 1 and then to the second input of the first register 9 (shift register). In addition, the clock signals from the output of receiver 1 are sent to the input of divider 8. As a result, 9 is written on Perzom register . the code signal completely reflects the signal transmitted over the communication line, i.e. the high level signal will be

30, the unit state of the bits of the register 9 corresponds to, the lower level signal is H, y.nei3oe. When writing to the register 9 the values of eight half-cycles of the information signal are made

2 of his condition

In the transmission mode via the communication line, information is not compressed, polling occurs via the second key block 11. The polling pulse is generated by degrading Q or the clock frequency with a divider 8, made in the form of a three-bit chip. who is the counter From the output of the divider 8, the pulse passes through the second element I 6 and enters the interrogation of the second block 11 of keys. The second element And 6 is at this time open, whereas the first element And Zakrp-, since there is no signal at the device input about the mode of operation with information transmitted with compression.

The information inputs of the second block of 11 keys are connected to all even register bits 9, starting at 55 of its input. As a result, at the output of the second key unit 11, a four-bit parallel code of the received information is generated. From the exit

3

the second key block 11 is a four-bit code signal through the second register 12 is output to the output of the valve.

In the mode of receiving information transmitted with compression, the first key block 10 is polled by a polling pulse received from the first AND 5 item opened in this mode. The information code signal from the outputs of the first key block 10 is fed to the input of block 14 EXCLUSIVE OR, which prepares the received code that information to its decoding.

The inputs of each of the elements 14.1-14.7 EXCLUSIVE OR signals of the state of each of the two adjacent bits of register 9 are received: 1-2.2-3.3-4.4-5, etc. The code signal obtained at the output of elements 14.1-14.7 is recorded in register 15 (shift register), in which the frequency of synchronization pulses arriving at the second input of the device provides for a cyclic shift of information. At the same time, the code signal from the output, the driver 16 of the feedback signal, is recorded in the lower bit of register 15

The shift pulses to the input of register 15 pass through AND 18, the first input of which supplies a signal from the output of the decoder 17 through the HE 19. The feedback signal is generated in the driver 16 from the signals of the first and last bits of the register 15 in such a way so that at the output of the imaging unit 16, a code unit occurs in cases when the high order of the dereg register 15 is written down one, or zero - in the low order.

The shift is carried out until a certain code is reached at the input of the decoder (in the considered example, in the 1st, 2nd, 6th and 7th bits, starting from the youngest, the code 11110 should be set) . As a result, element 18 is closed, and the signal from the outputs of the remaining register bits (in the considered example, the 3rd and 5th bits) is fed through register 12 to the output of the device together with the signals from the outputs of counter 20, as a decrypted signal received that information. At the entrance of the counter, 20 poda

ten

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20 25

incoming

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shift pulses, to the input of register 15.

Thus, the proposed device provides digital reception. information transmitted over a standard communication channel in two modes: both in the normal mode of information transfer and in the mode of information transfer with compression. The main technical and economic effect of the application of the proposed device lies in the fact that this device provides the ability to work in a multi-subscriber communication system with subscribers that allow compression of information, and with conventional standards.

Claims (3)

1. A device for receiving digital information, comprising a serial code receiver, the first and second inputs of which are respectively the first and second inputs of the device, the first and second outputs of the serial code receiver are connected respectively to the first and second inputs of the first register, characterized in that the purpose of expanding the area;: device use by receiving both uncompressed and compressed digital information, key blocks, AND elements, a NOT element, a divider, a code converter, and a second register are entered into it page, the first output of the serial code receiver is connected via a divider to the first input of the first element, and through the element is NOT connected to the first input of the second element, the outputs of the first and second elements are connected to the control inputs of the first and second key blocks, respectively; the outputs of the first register are connected to corresponding information inputs of the first and second key blocks, the outputs of the second key block are connected to the first inputs of the second register, the outputs of the first key block are connected to the first inputs of the pre photoelectret code outputs are connected to second inputs of the second register, the second inputs of a serial receiver and the code converter are combined second inputs of the first and second AND gates are combined and the third input device, the outputs of the second register devices are output. The device of claim 1, wherein the serial code receiver comprises a differentiation unit, an AND element, a differentiator output connected to the first divider input, the output of which is connected to the first input of the And element, the combined input of the differentiation unit and the second input of the element Both the second input of the divider are respectively the first and second inputs of the receiver of the serial code, the outputs of the divider and the And element are respectively the first and second outputs of the receiver of the serial code, 3. The device according to claim 1j, characterized in that the code converter contains a block of elements EXCLUSIVE: OR, register, deshis Composer B, Borodin N.Yatsola editor Tehred M.Hodanich Proofreader-i.Musk Order 4331/52 Circulation 515 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035r Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 the phrator, the element And, the element NOT, the signal conditioner and the counter, the outputs of the block of elements EXCLUSIVE are connected with the corresponding first:; register moves, the first and second outputs of which are connected to the corresponding inputs of the decoder, the outputs of the bits of the registers are connected respectively to the first and second inputs of the signal conditioner, the output of which is connected to the second input of the register, the descriptor's output is NOT connected to the first input of the AND element, the output of which is connected to the third register input and the counter input, the inputs of the EXCLUSIVE OR block and the input of the AND element are respectively the first and second inputs of the code converter, the second register outputs and the counting outputs are code converter outputs.