SU1481831A1 - Receiver of adaptive data from distributed units - Google Patents

Abstract

This invention relates to telemechanics. The purpose of the invention is to increase the speed and functional reliability of the device. The device contains a clock pulse generator 1, a pulse distributor 2, a switchboard, decoders 4 and 5, a group of elements 6 ₁ -6 _N AND, a group of elements 7 ₃ -7 _N mappings, counters 8 and 9, elements 10 and 11, elements OR 12 and 13, delay element 14, information channels 15 ₁ -15 _M , comparison unit 26, decoders 27 and 28. Each information channel contains a linear block 16, a reception and control block 17, elements 18-21, a memory block 22, element OR 23, counter 24 and timer 25. 2 Il.

Description

The invention relates to telemechanics and can be found and used in telemetry systems, automated process control systems, data transmission equipment.

The purpose of the invention is to increase the speed and increase the functional reliability of the device.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 - timing diagrams for the operation of the device.

The device contains a generator of 1 clock pulses, a distributor of 2 pulses, a switch 3. the first 4 and second 5 decoders, a group of elements - a group of elements 7, -7m

comrade 6, -6,

the display, the first 8 and second 9 counters, the first 10 and second 11 elements AND, the first 12 and second 13 elements OR, delay element 14, information channels 15, -15, each of which contains a linear unit 16, a reception and control unit 17, the first 18, the second 19, the third 20 and the fourth 21 elements I. the memory block 22, the element OR 23, the counter 24 and the timer 25, the comparison block 26, the third 27 and the fourth 28 decoders.

The device works as follows.

From the communication channels to the inputs of the switch 3, which are the information inputs of the device, sporadically (only when the state changes), information is received about the state n of the remote distributed objects. The lack of information (changes in the state of objects) is accompanied by the presence of signals of only one polarity in the communication channels: 1 or O. The information is connected with the alternation of 1 and O. Switch 3 connects the communication channels to the receiving information channels 15, - 15 devices, the number of which is less than the number of communication channel (t n). The operation of information channels 15, -15 is provided by m sequences of clock pulses shifted in phase one relative to another, which are formed by distributor 2 pulses from the reference clock sequence of clock generator 1 with a period of Ј0 (Fig. 2. where a is the pulse at the output of generator 1 , 6- per

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second, second, r - i-th, d - m-th outputs of the distributor 2 pulses).

The process of receiving information from objects in the device is divided into three stages: connecting communication channels to free information channels, analyzing the availability of information on communication channels, and receiving and processing information.

The main unit coordinating the operation of the device at the stage of selecting and connecting communication channels to free information channels is counter 8, the capacity of which is equal to the number of communication channels n (log n + +1) of the triggers, where is a whole part of the logarithm. Each state of the counter 8 corresponds to the binary code of the communication channel number.

. Let counter 8 receive the next bostate corresponding to the binary code of the number of the first communication channel (Fig. 2, e - 1).

The code of the number of the first channel from the output of the counter 8 enters the comparison unit 26, the third decoder 27 and the recording inputs of the memory channels 22. At the other input of the comparator unit 26 and at the input of the second decoder 5, with each clock of the reference frequency of the generator 1, the code values of the numbers of the communication channels connected to them, which are stored in the memory blocks 22, are received through the elements AND 18 information channels. Simultaneously with the beginning of the comparison cycle, the communication channel number codes begin the counting of the number of generator pulses 1 by the second counter 9.

If during the time of action m pulses of the generator 1, i.e. During the cycle of polling all the memory blocks 22, the block 26 compares the matching of the communication channel number codes (in this case, the first channel, Fig. 2.g), then the output of block 26 generates a signal that through the second element OR 13 enters the element 14 delay and resets the counter 9 to the initial (zero) state (Fig. 2, h). From the output of the element 14 with a delay signal (Fig. 2, m) passes to the input of the first counter 8, transferring it to the next state corresponding to the second traffic channel (Fig. 2, e - 2). A new comparison cycle begins.

codes of communication channels in block 26.

If none of the m pulses of the generator 1 block 26 recorded a coincidence of the numbers of channels, i.e. the fact that the communication channel is not connected to any 15.15 t information channel is established, then the counter 9 continues to count the pulses of the generator 1 (Fig. 2, s - S, Ј0, SaЈ0). Starting from (m +, 1) -th to -2-th pulse, the fourth decoder 28 (Fig. I) is constantly producing a signal connected to the output of counter 9. This signal goes to one of the inputs of the And 11 element. To other inputs the latter is connected to the output of the clock pulse generator 1 and the output of the decoder 5, on which signals appear only when the decoder 5 arrives at the input of memory channels 22 of the Formation channels 1-5, -15 zero code combinations of the communication channel numbers (Fig 2, k - the i-th and t-and information channels are initially free). At the first coincidence, at all inputs of the second element I 11 of the signals at the output, a pulse is formed (firm. 2, l), which performs the following operations: through the element OR 13, the counter 9 is reset to the zero state; A free memory block 22 of information channels 1 5, -15 t is selected by coinciding this pulse with a pulse. the distributor 2 in the corresponding element And 20; through the element OR-13, the pulse arrives at the delay element 14 and further to the first element AND 10, creating the prerequisites for transferring the first counter 8 to the state corresponding to the number of the next communication channel.

Impulse from the output element and 20

allows writing the code of the communication channel number from the output of the counter 8 to the free memory block 22, starts the timer 25, sets the counter 24 to the initial zero state, and also goes to the corresponding control input

switch 3. At the other control input of the latter, corresponding to the number of the selected communication channel, a signal from the output of the third decoder 27 is in effect at that time. This signal is generated by reading the counter 8. The simultaneous action of the signals on the two control signals

Q j 0 5 Q

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the inputs of the switch .3 connects the selected communication channel to the selected free information channel. ig. 2 illustrates the cases of connecting the second drop of communication to the i-th and third communication channel to the gp-th information channels of the device.

If at this moment there is at least one more free information channel in the device and, accordingly, a free memory block 22, then this is indicated by the corresponding fourth element 21 connected to the second output of memory block 22. The signal formed by the output of the AND 21 signal through the first OR 12 element (Fig. 2, n) is fed to the first input of the AND 10 element, thereby allowing the pulse to pass from the input delay element 14 to the counter 8 (Fig. 2, o). Counter 8 is transferred to a new state corresponding to the next communication channel (Fig.2, e). A new stage of selecting and connecting another communication channel to the free information channel 15, -15t begins.

No free information channel remained in the device, then at the output of the first element OR 12 there is no signal and the pulse from the delay element 14 does not reach the input of the counter 8 (Fig. 2, m) - the third pulse. Counter 8 retains its state until the first release of any information channel (Fig. 2, e is the state corresponding to channel N ° 3).

The second stage — analysis in the communication channel — is carried out in each information channel. 15, -15t with the help of a linear block 16, a receive-and-control block 17, a timer 25 and a counter 24. Each linear block 16 matches the information channel with a duplex channel communication and performs signal conversion: demodulation (reception) and modulation (transmission).

The code packets received from the communication channel come from the linear unit 16 to the receiving and controlling unit 17, the counter 24, and also to the modulator of its own linear unit 16, from which they are sent on the reverse link to the object (information feedback) . In block 17, code sends are regenerated, clock and cycle phasing is performed, and the code combinations are checked for consistency with the error-correcting code. The counter 24 counts the number of edges of the received parcels during the control time interval T0, which is set by timer 2.5. The value of TO is selected based on the statistical characteristics of the coding of information so that the number of edges in the presence of information in the communication channel during the time interval T0 is not less than a certain threshold R. Timer 25 in the simplest case is an ordinary binary counter, with a capacity

TO

That / h

where fK is the duration of the code combination.

The pulses corresponding to the beginnings of code combinations are fed to the input of timer 25 from the receiving and monitoring unit 17, after the time T0 expires, the timer polls counter 24 and if during the TO time the number of fixed edges of the parcels did not exceed R, the counter 24 generates a No Information signal. This signal, through the OR element 23, erases the communication channel number in memory block 22, as a result of which the information channel becomes free again and ready to analyze and receive information from the next communication channel.

If the number of edges in time T0 has exceeded or reached the value of R, then when polling counter 24, the signal at

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its output is absent, which indicates the presence of information in the communication channel, and further reception and processing of the message from the object continues.

The third stage - the actual reception and processing of information - begins after the phasing in cycles and cycles in block 17 of reception and control. With each correct reception, code combinations from the first output of block 17 are read in parallel code to decoder 4. The result of decryption passes through the corresponding AND group into the display element 7, -7 "by displaying a resolution signal to the second input of the AND 6, 6p with one of the first exits

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The second decoder 5. This is ensured by the fact that the input of the decoder 5 at the time in question is connected via an AND 18 element to the output of the corresponding memory block 22 in which the code of the communication channel number (object) is stored. Due to the fact that the power clock sequences in information channels 15, 15, are separated in time, the device eliminates cases of superposition of two or more combinations received from different objects, i.e. Cases of false 5 decryption of the decoder 4.

After the reception and processing of all information code combinations from the object, the service combination of the end of the message arrives, which is decoded in the usual way by the decoder 4, the corresponding pulse from the second output of the decoder 4 is selected in the corresponding information channel And 21, which is output through the OR 23 element erasing the code of the number of the connected communication channel in the memory unit 22, and the information channel is released to receive information from another communication channel.

When all information channels in the device are busy receiving information from objects, counter 8 is in the state corresponding to the last connected communication channel. Comparison unit 26, after every mt of acts of generator 1, generates a signal for matching the number of this communication channel with the code stored in one of memory units 22 of information channels 15, -15W. The pulse from the output of the block 26, each time after the time interval m T0, resets the second counter 9 to the initial state, the decoder 28 does not generate a signal at its output. From the output element 14 of the delay pulses to the input of the counter 8, is not received. With the release of at least one information channel at the input of element 10, a signal appears that permits the passage of a pulse from the delay element 14 to counter 8. A new stage of selecting and connecting the next communication channel for analyzing and receiving information begins.

The proposed device eliminated two-stage switching ko0

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communications are sent first to the blocks that only determine the presence or absence of information, and then, if there is information, to the free receiving equipment, the analysis of the availability of information in the communication channel and the subsequent reception and its processing are performed sequentially-in parallel only in the information channel.

Claims (1)

Invention Formula An adaptive device for receiving information from dispersed objects, containing a clock pulse generator, the output of which is connected to the input of the pulse distributor, the same outputs of which are connected to the first inputs of the receiving and control units of the same information channels, the switch, the information inputs of which are the outputs of which are connected to the inputs of linear blocks of similar information channels, in each of which the output of the linear block is connected the second input of the reception and control unit, the corresponding output of the group of the reception and control unit of all the normal channels are combined and connected to the corresponding inputs of the first decoder, the corresponding outputs of the group of which are connected to the combined corresponding inputs of the group of each element And group, the corresponding outputs of each element And group are connected to the corresponding the inputs of the same display elements, in each information channel, the memory block, the direct outputs of which are connected to the corresponding The inputs of the group of the first element I, the same outputs of the first elements AND of all information channels are combined and connected to the same inputs of the second decoder, the corresponding outputs of the group of which are connected to the inputs of the corresponding elements AND group, the inverse outputs of the memory block in each information channel are connected to the inputs of the second element And, the output of the second element And the corresponding channel is connected to the corresponding input of the first element OR, the output of which is connected to the first input of the first element And, second And the second element the output of which is connected to the first input of the second OR element, the output of which is connected to the input of the delay element is the first counter, on each information channel the third and fourth element is AND, the OR element, characterized in that, in order to increase the speed and increase the functional reliability of the device, A second counter, a comparison block, a third and a fourth decoder are entered into it, each information channel is a counter and a timer, the output of the clock generator is connected to the first inputs of the second counter and the second element, And, The second input of which is connected to the output of the second decoder, the output the delay element is connected to the second input of the first element And, the output of which is connected to the input of the first counter, the corresponding outputs of the group of which are connected to the corresponding first inputs of the block comparison, with the combined corresponding inputs of the memory block group of each information channel and with the corresponding inputs of the third the decoder, the corresponding outputs of which are connected to the corresponding first control inputs of the switch, the combined corresponding outputs of the first element AND of each information channel are connected to the corresponding second inputs of the comparison unit, the output of which is connected to the second input of the second element OR, the output of which is connected to the second input of the second counter, whose outputs through the fourth decoder are connected to the third input of the second element And whose output is connected to the combined first inputs of the third element And of each information channel, the same outputs of the pulse distributor connected to the input of the first element And, the second input of the third element And, the first the input of the fourth element and information channel of the same name, the output of the first decoder is connected to the combined second inputs of the fourth element AND of each information channel, in each information “ linear channel, the output of the linear unit is connected to the first input of the counter, the output of the receiving and control unit is connected to the first input of the timer, the output the counter, the output of which is connected to the first input of the OR element, the second input of which is connected to the output of the fourth AND element, the output of the OR element is connected to the first input Ta I is connected to the second input of the memory unit, the third input of the counter, the second input of the timer, and the corresponding second control input of the switch. FIG. 2