RU1807509C - Adaptive device for data reception from dispersed entities - Google Patents

Abstract

The invention relates to telemechanics. The purpose of the invention is to increase the speed, information flexibility and reliability of collecting information about the state of n remote dispersed objects combined in two groups. The first group consists of m objects with higher informational activity, and the remaining n-ni objects are combined in the second group. The objects of the first group are provided with the advantage of connecting the corresponding input units through the switch to the receiving information channels. Information from the objects is transmitted via communication channels operatively. Using the timer, offset time intervals Ti are continuously generated, during which the presence of information in the communication channels with the issuance of the control signal 1 in case of its detection is analyzed in the input units. The binary counter 16, whose capacity is n, through the decoder sequentially polls the And elements. When the polling pulse coincides with the signal 1 of the presence of information at the other input of the element, the counter stops and the corresponding input unit is connected through the switch to a free information channel to process the received message. The priority of the first group of objects is ensured by combining the output control signals of the input blocks by the IL element and by supplying the prohibition signal generated by it to the I elements. 2 zpf-files, 3 ill. THX

Description

The invention relates to telemechanics and may find application in automated process control systems and data transmission equipment.

The purpose of the invention is to increase speed, information flexibility and reliability.

In FIG. 1 shows a functional diagram of the proposed device; in FIG. 2 - input unit; in FIG. 3 - information channel.

The device contains a clock generator 1, a timer 2, input blocks

3t-3m and Зщ-И - Зп, 4 pulse distributor, information channels 5i-5m, switch 6, first 7, second 8 and third 9 decoders, first South lOni second Yush + 1 -Up. Third 1.11-11sh and fourth: 11п1 -I-11p group of AND elements, elements 12i- I2n-i and 12sh +1 12p display, first 13 and second 14 OR elements, delay element 15, counter 16, first 17 and second 18 AND elements, NOT element 19 and OR element -HE20.

Each input unit (Fig. 2) includes a linear unit 21, an OR element 22, a counter 23, and a trigger 24.

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31807509 4

Each information channel 5i-5m of the display 12i-12Hz and 12ni + 1-12p Control- (Fig. 3) contains from the first to the third electronic outputs of the output blocks of the first cops And 25-27, the block 28 of the reception and control groups are connected to the first inputs and the memory unit 29 of the elements of the same name And the third corpse are the output of the generator 1 clock pulses 11r-11tl1 and through the element OR NOT 20 with the sov is connected to the input of the timer 2 distributed-combined inputs of the elements and the chitter 4 pulses and element And 18. The output of the fourth group 11shch +1 - 11 „; Control of timer 2 is connected to the first control

the input of each input unit is 3–3nl, with EXIT ° YES OF INPUT BL ° K ° IN VT ° R ° AND FUPPY

„1PZgi + 1 - 3P1 are connected to the first inputs

3ni-N-3P first information input and U-g,

elements of the same name And the fourth group output of which are respectively Пы 11щ +1 11п. The outputs of all elements by the input and output of the first (1-ni) and second .. ,, ... ..., (pm-n) groups of objects. The second information is 11l mi-11P1 + i-11n. through the IL element And the input and output of each input block, 14 are connected to the input of the element NOT 19 and connected respectively to the first 15 input of the AND element 17, the second inputs of the information output of the second which is connected to a separate output of the group and the input of the first group of inputs com-encoder 8. The output of the element And 17 e-mediator. The pulse distributor 4 is named with the combined second et m outputs (), each output being the control information inputs connected to the clock input of the same name 2 channels 5i-5m and the first input of the first information channel 5i-5m. Each element is OR 13. The output of the element NOT .19 of channels 5i-5m has, in addition, an information connection to the first input of the element AND 1.8, an input input, the first and second control of which is connected to the second input, inputs, a group of address inputs , group. element OR 13. The output of the OR element 13 is addressable and the group of information output through the delay element 15 is connected to the inputs. The information input of block 5i-5ffl co-A ° m counter 16. The outputs of which are connected with the same name are the first to the address inputs of each group of information outputs of the commutation information channel and the inputs of the third torus 6 and its second input of the same name. Decryptor 9. Decryptor 9 has two groups of information inputs. Control - JU group of outputs. The outputs of the first group are connected to the single output of the block 5i-5m: they are connected to the same name controlling the input of the first group of inputs of the second group of the switch 6 and the second control inputs of the switch 6. The same inputs of the same elements And the name outputs of the third information groups groups 11p-11sch. the outputs of the information channels 5i-5m The outputs of the second group of the decoder 9. are connected and connected to the inputs are first connected to the same controls of the decoder 7, and the same outputs of the third group of the switch 6 and. groups of address outputs of channels 5i-5m by second inputs of the same name are united and connected to the inputs of the second. And the fourth group 11 ni +1 - Ip In each decoder 8. Separate output of the decoder-input unit 3i-3n the first input and output of the torus 7 is connected to the combined first linear block 21 are the corresponding control inputs of the information ka, the first information input and the mals, the second control inputs and the second input and the second output, which are also combined and connected to the second information input and output ne the first element And 17 and the first house of the input block. The second input of block 19 to the input of the OR element 13. The decoder 7 is connected to the input of the counter 23, the input resets a group of outputs, which parallel connection to the output of the element is connected to the inputs of the first IOi-OR OR 22. The first and second inputs of this elec the second 10P1 + 1-1 On of the element groups I. The 50 entries are respectively the first and the encoder 8 has two output groups, the second by the input control inputs which are connected respectively to the unit. The output of the counter 23 is connected to the inputs of the same name of the trigger 24. The reset input of which is connected by 101I 10P1 and TOSh + i-10n is the second with the second input of the OR element 22. The control inputs of the same name 55 The trigger output a is connected to the third input blocks 3, - Zsch, Zsch +1 - ZnVykho-BX ° W element OR 22 and is the control. input output block. ,

Each element I0i- in each information channel 10nin1pn1 + .. i-10n is connected to the corresponding - - 5l-5m the first inputs of the first25 and second26

the input inputs of the same element elements And, block 28 reception and control and

the input of the third element And 27 are combined and are the clock input of the information channel. The second inputs of block 28 and the elements And 25 and 26 are respectively information, the first and second control inputs of the information channel. The outputs of the elements 25 and 26 are connected respectively to the first and second inputs of the memory unit 29, the outputs of which are connected to the inputs of the third element And 27. The output of the element And 25, the outputs of the block 28 of the reception and control, the outputs of the element And 27 and the inputs of the group of the block 29 of the memory are respectively the control input, information and address outputs and address inputs of the information channel.

It should be noted that the spatial arrangement of the inputs and outputs of the input unit 3 in FIG. 2 and information channel 5 in FIG. 3 clearly corresponds to the inputs and outputs of the blocks and 5Н5т on

FIG. 1;

The device operates as follows.

Information on the state of objects of the first and second groups, respectively, is received sporadically at the first information inputs of the blocks ZTZzci 3ni + i-3n through communication channels. In the absence of information - changes in the state of the object - signals of one polarity O or 1 or service code combinations at rest with a minimum number of polarity reversals are constantly transmitted in the communication channel from it. The presence of changes in the state of objects is accompanied by the transmission of information code combinations with a large number of polarity reversals per unit time. The structure of code messages from all objects is the same. Each input block ЗЗ-Зп carries out the interface with the forward (demodulation) and reverse (modulation) communication channel and continuously analyzes the presence of information in the communication channel from the object by counting the number of changes in the polarity (edges) of the signals. The analysis time Ta is a constant, is selected based on the statistical properties of the information for all blocks 3-3 the same, and is continuously formed by timer 2 by dividing the reference frequency f of the clock generator 1. The division coefficient Kd is equal to:

To T. t 3 Ta. where is the pulse repetition period of generator 1.

Timer 2, at time intervals Ta, each time sets the edge of the signal counter in the input blocks to its initial state. If during the time T Ta in the 1st (m) or jth (u + 1 jn) communication channel, respectively, of the first or second group, the presence of information is detected, then a constant output is generated at the control output of the corresponding input unit 3i (3j) level 1 signal. The pulses from the output of the generator 1 also arrive at the inputs of the element And 18 and the pulse distributor A, which generates m clock sequences that ensure the operation of information channels 5i-5m. In the absence of signals 1, the information is present at the control outputs of blocks 3i-Zsch and 3ni Ch-1 - Zn at the outputs of the elements And 11- 11ni and 11ni +1 - 11p. level O signals are generated. These signals, after being combined by the OR element 14, are inverted by the HE 19 element and allow the clock pulses of the generator 1 to pass through the And element 18, the OR element .13 and the delay element 15 to the input of the ring counter 16. The counter capacity is n, and the number of binary cascades of L is logan (if logan is a fractional number, then L is 1od2G +1, where the expression in square brackets is the whole part of the logarithm). Each counter state 16 corresponds to a binary code of a communication channel number. This code is decrypted by the decoder 9. The signals from the outputs of the decoder 9, corresponding to the numbers of communication channels (objects) of the first group, are fed to the inputs of the elements And 11t 11sc. The elements And I1ni + r 11n correspond to the numbers of the channels of the second group. If the signals at both inputs of an element And 1 t 11ni coincide, for example, an element of the third group 11, which occurs when there is a signal 1 at the control output of the 1st input block, element 11 | forms a signal that passes through the OR element 14. This the signal is inverted by the element HE 19 and prevents the further passage of the clock pulses of the generator 1 through the element And 18 to the counter 16, which stores the state corresponding to the number of the i-ro communication channel. From this moment, the stage of searching for the free information channel 5i-5m and connecting to it via the switch 6 the second information outputs and the input of the I input block () begins. In occupied 5t5p information channels, binary codes of the numbers of input blocks of ZtZp connected to them are stored. in free - zero code combinations. This code is read in parallel to the decoder 8

at each arrival at the clock input of the information channel 5i-5m of pulses from the corresponding output of the distributor 4. If there is an e-th (1: е т) free information channel, the decoder 8 generates a signal with a duration of a clock pulse, which through an open element And 17 is fed to the second control inputs of the information channels and to the input of the OR element. 13, After the selection of the control signal, the number of the 1st communication channel number is recorded and stored in the e-information channel after the control signal is selected. address inputs from the counter 16. In addition, a pulse is generated at the control output of the e-th information channel, which is fed to the e-th input of the first group of control inputs of the switch 6. The simultaneous action of this pulse and the signal from the decoder 9 at the i-th input the second group of control inputs of switch b provides the connection of the i-ro input unit to the e-th information channel. Meanwhile, the pulse from the output of the AND element 17 also passes through the OR element 13 to the delay element 15. Shortly after the delay time T3, t0, element 15 generates a pulse, which puts the counter 1 b into the state corresponding to the (1 + 1) th communication channel. If all the information channels 5i-5m are occupied, the counter 16 remains in the state corresponding to the number of the 1st communication channel until at least one of the channels 5i-5m is freed. After connecting the 1st input block in the e-th information channel, reception and processing of information from the object begins. In addition, the demodulated code messages are sent through the switch 6 to the second information input of the 1st input unit and through its modulator to the reverse communication channel to the ith object. Thus, from this moment, informational feedback is provided in the duplex communication channel between the ith object and the device. In the information channels 5i-5m, clock and loop phasing are carried out and the correspondence of the received code combinations to the error-correcting code is checked. With each correct reception, the code combinations of the primary K-bit code are read in parallel to the input of the first decoder 7. Since the working clocks of the information channels are spaced out of phase, the outputs of the same group of information outputs of the channels 5i-5m, as well as the address outputs from them, form common bus. Decoder

0

7 provides the results of decoding through the elements And 10i- 10sc, 10ni + 1 - 10n to the elements 12i- 12n- | and 12Hz + 1 - 12n mappings. The correct passage of information to the elements 12i-12sc and 12ni + i - 1 2p is ensured by the selection of this element by supplying an enable signal to the control input of the corresponding element And 10i-10ni, 10p1-N - 10P from the outputs of the first and second groups of Decoder 8, which decrypts currently the binary code of the communication channel number

- (input unit) recorded in the memory of the information channel 5i-5m. At the same time, the pulse from the output of the decoder 8 is fed to the second control input of the input unit 3i-3ni of the same name and

0 3ni +1 - Zn and transfers it to its initial state. In this way, the availability of information and the connection of those communication channels that are already connected to the 5i-5m information channels are excluded from the analysis process. The first reset pulse is generated shortly after after connecting the communication channel to its own. about the free information channel 5i-5m, i.e. almost instantly compared

0 with the information transfer rate in the communication channel and the analysis time Ta.

At the end of the transmission of information from the objects, the rest code combinations come in, which are also decrypted by the decryptor 7. The decryption pulses of these combinations from the separate output of the decryptor 7 are selected in the corresponding information channel 5i-5m and erase the connected number code in it

0 communication channels. From this moment, the corresponding information channel 5i-5m is ready to connect another communication channel.

Priority to the objects of the first group is ensured by combining the output control signals of the input blocks 3i-3ni with the OR-NOT 20 element and by supplying the inhibit signal generated by it to the elements And 11sc + 1-11p corresponding to the objects of the second group. In this case, the counter 16. from the state corresponding to the (u-I) th communication channel is idle until the fifth, i.e. even if there are control signals at the outputs of the input units, their connection to the information channels 5i-5m is excluded. As soon as the inhibit signal is removed from the inputs of the And 11sc-H-11p elements, polling and connection of the communication channels of the second group to the information channels is allowed in the same way as for the first group of channels.

In the proposed embodiment of the input unit 3 (Fig. 2), the number of edges of the received code packets is counted with a counter 23 connected to the output of the linear block (modem) 21. When the counter is full, it generates a signal that puts the memory trigger 24 in state 1. This signal is fed to the control output and simultaneously through the OR element 22 resets the counter 23 to the zero state. Trigger 24 is reset when pulses arrive from decoder 8 via the second control input of input block 3. Counter 23 is reset to the zero state from the OR element 22 by pulses from timer 2 (the first control input of the input block) and from decoder 8 (second control input).

In the information channel 5 (FIG. 3), messages are encoded via the information input to the reception and control unit 28, in which clock and loop phasing is carried out, checking the received code combinations for compliance with the error-correcting code, removing excess code bits and issuing K-bit combinations of the primary code for information outputs. The operation of block 28 is provided by clock pulses arriving at the clock input of the information channel. The same clock pulses carry out a clock selection of the recording permission signals and erase the channel number code. Communication to the memory block 29, respectively, received via the second and first control inputs to the I and 26 elements. The impulse from the output of the I element 26 also goes to the control output of the information channel 5. The memory unit 29 in the simplest embodiment can consist of L memory triggers, pulses are sent to the input of each trigger via the corresponding bus of the address inputs of the information drop. Through AND element 27, the communication channel number code is read by a parallel code at the address outputs with each clock pulse,

Claims (3)

Thus, in comparison with the prototype device, the proposed device-1 reduces the search time for the communication channel by the presence of information by a factor of 1-n. In this case, the communication channels from the objects of the first group in the presence of free information channels are connected to the latter with virtually no delay. Communication channels of the second group of objects in which information is found can only be connected to free information channels if there is no information in the unconnected channels of the first group. This is the property of a higher information flexibility of the device. And finally, in the proposed device, there is a constant interface with channel forming equipment, which increases the reliability of collecting information from dispersed objects. The formula is invented and 1. An adaptive device for receiving information from dispersed objects, comprising a clock pulse generator, the output of which is connected to the inputs of a timer and a pulse distributor, the outputs of which are connected to the clock inputs of information channels, the first input and output of each of which are connected respectively the first output and input of the switch, the first and second OR elements, the output of the first OR element is connected through a delay element to the counter input, the outputs of which are connected to the corresponding the inputs of all information channels and the inputs of the first decoder, the outputs of which are connected to the corresponding control inputs of the switch, the second and third decoders, the outputs of the first group of the second decoder and the outputs of the third decoder are connected respectively to the inputs and inputs of the group of elements of the first group, the outputs of which are connected with the corresponding inputs of the corresponding display elements of the first group, the control output of the third decoder is connected to the second inputs of all information cameras, als, the outputs of the first and second groups of each of which are connected respectively to the same inputs of the second and third decoders, characterized in that, in order to increase speed, information flexibility and reliability, input blocks, the second, third and fourth groups of AND elements are introduced into it , the element OR NOT, the element NOT, the elements AND and the second group of display elements, the inputs and inputs of the group of elements AND of the second group are combined respectively with the outputs of the second group of the second decoder and the inputs of the group of elements of the first groups, outputs of elements And the second group are connected to the corresponding inputs of the corresponding display elements of the second group, the first input and output of each of the input blocks are the input and output of the device, the second input and output of each input block are connected respectively to the second output and second input of the switch; the timer output is connected to the clock inputs of the input blocks, the third outputs of which are connected to the first inputs of the corresponding elements of the third and fourth groups, the outputs of the first decoder connected to the second inputs of the corresponding AND elements of the third and fourth group, the outputs of which are connected to the corresponding inputs of the second OR element, the output of which is connected to the first input of the first AND element and through the element NOT to the first input of the second AND element, the output of which is connected to the first input of the first OR element, the output of the second decoder is connected to the second input of the first AND element, the output of which is connected to the third inputs of all information channels and the second input of the first OR element, the output of the clock generator of the second pulses is connected to the second input of the second AND element, the inputs of the OR element are NOT combined with the first inputs of the AND elements of the third group of the same name, the output of the OR element is NOT connected to the third inputs of the AND elements of the fourth group, the outputs of the first and second groups of the second decoder connected to the third inputs of the corresponding input blocks. 2. The adaptive device according to claim 1, wherein each input unit comprises a trigger, a counter, an OR element and a linear unit, the first and second inputs and the outputs of which are, respectively, the first and second inputs and outputs of the block, the first and second inputs of the OR element are clock and the third inputs of the block, the output of the OR element is connected to the reset input of the counter, the input of which is connected to the second output of the linear block, the output is connected to the trigger input, the reset input of which is connected to the second the input of the OR element, the third input of which is connected to the output of the trigger and is the third output of the block. 3. The device according to claim 1, with the proviso that each information channel contains a memory unit, AND elements and a reception and control unit, the first inputs of the reception and control unit and the first and second AND elements are combined with the entrance of the third element And and are a clock input information channel, the second inputs of the reception and control unit, the first and second elements AND are respectively the first, second and third inputs of the information channel, the outputs of the first and second And elements are connected respectively to the first and second inputs of the memory unit, the outputs of which are connected to the inputs of the third element And, the output of the second element And, the outputs of the reception and control unit and the third element And, the inputs of the group of the memory block are respectively the first output, outputs of the second and first groups, address inputs of the information channel. 5 ° g / g. At iynp Ј. " 1 . ftfff ivutfi. Sttref V - +. Јt / fi 2ynp. FIG. 2 fyp. ttrreff Totfm w t.j JldpetH. 6ttrerk JfyfCH. . IreJ 2unf. teoJ Unp. & xod 28 and up. & nrofa