RU1807510C - Device for receiving information from distant dispersing objects - Google Patents

Abstract

The invention relates to telemechanics. The purpose of the invention is to increase speed and reliability. The device contains a clock, counters, input blocks, a pulse distributor, information channels, a switch, decoders, groups of AND elements, display elements, an OR-NOT element, an OR element, AND elements, a delay element, an NOT element, a trigger. Two groups of input blocks of the receiver interface the device with communication channels from n objects and continuously analyze in them the presence of information sporadically transmitted from rn priority objects and P2 (n-rz) less important objects. Using a counter having a capacity equal to the number of objects n, and two groups of elements AND, the input blocks are constantly searched for, by which the presence of information is recorded, and they are connected through the switch to the receiving information blocks. The absolute priority for the connection is presented to the input blocks of the first group , while the input blocks of the second group can only be connected to free information blocks during periods of lack of information from the objects of the first group. 2 C.p. f-ly, 3 ill. with

Description

The invention relates to telemechanics and may find application in automated process control systems, data transmission equipment with various organization of polling information channels.

The purpose of the invention is to increase utilization, speed and reliability.

In FIG. 1 shows a functional diagram of the proposed device, which contains a clock generator 1, first 2, second 3 and third 4 counters, the first 5i-5ni and second 5ni -I-5P groups of input units, a 6-pulse distributor, information channels 7i-7m, a switch 8, first 9, second 10 and third 11

decoders, the first 12sh, the second 12sh + 1-12p, the third 13i-13ni and the fourth 13Hz of the group of And elements, the first and second 14ni + 1-14p of the group of display elements, the element OR NOT 15, the first 16, the second 17, the third 18, fourth 19 and fifth 20 OR elements, first 21, second 22, third 23 and fourth 24 AND elements, delay element 25, trigger 26, and HE element 27.

The composition of each input unit 5 (Fig. 2) includes a linear unit 28, an OR element 29, a counter 30, and a trigger 31.

Each information channel 7 (Fig. 3) contains a first 32, a second 33, and a third 34 AND elements, a receiving and monitoring unit 35, and a memory unit 36.

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The output of the clock generator 1 of the same-pulse elements I12sh + i-12n, the second bus is connected to the inputs of the first counter 2, the red control inputs of the 6-pulse distributor, the second input input blocks of the second group house 22 and the first input of the third 235ni -h and, in addition, through the element OR of the elements I. The output of the counter 2 is connected to 5 2o are connected to the second input by the elements, the first control inputs of the input clocks and 24. The outputs of each of the elements AND blocks of the first 5i-5ni and the second 5sh + 1-5p121 -12shchi 12shch + 1-12p are connected to the corresponding groups. The first information input and the corresponding inputs of the same element are the input block 51-5sh, 5sh + H5p vl - TOV displays 14g14sh and 14sh +1 -14P. 1- (Hz-m), (u + 1) - (p-m), respectively, are controlled by the outputs of the input blocks by the transition and the output of the receiver from the u object group | 51-5P1, connected to the first first and (P2-П-Щ) objects of the second group. The inputs of the elements of the same name And the third. The second information input and output of each 13 13 as well as JeM6HT of the input block are connected respectively. ....... ,,, - „, with informational names of the same name 15 OR NOT 15 - with the second inputs of the element-output of the second group and the input of the first AND and the fourth group 13„, + 1-13 “. Upp-groups of inputs of the switch. Distributing outputs of the input blocks, the second pulse body 6 has m outputs (), the groups 5sh + 1-5p are connected to the first ones. Each care is connected to the clock inputs, inputs of the elements of the same name And the same block 7i-7rn. In addition, 2 and the fourth group 13sh + i-13n. The outputs of all the inputs, each of the blocks 7i-7m has in-elements. H13i-13ni, 13ni through the formation input. The first and second up-element OR 19 are connected to the input elec- tric inputs, a group of address inputs, an element NOT 17 and a second input of the element And as well as a control output, an address group “5 21 the output of which is connected to the first outputs and the group of information outputs of the second element OR 17. The outputs of the moves. The information input of each element And 131-13shch,. in addition, through the block 7i-7m, the output element OR is connected to the same name OR 18 is connected to the first input of the first group of information outputs of the element And 22, the output of which is connected to the inputs of the switch 8 and its same name Q is connected to the input of the third counter 4. Output by the input the second group of information counter 4 is connected to the input of the trigger 26, inputs. The control output of each unit whose output is connected to the first input 7i-7m is connected to the same input of the per-element And 24, the output of which is connected to the first group of control inputs commutated to the second input of the OR element 17. The output of the torus 8. The same outputs of the group of element HE27 are connected to the second input of the information outputs of blocks 7i-7m of the element And 23, the output of which is connected to the combined and connected to the inputs by the first input of the OR element 16. The output of the decoder 9, and the outputs of the same name 16 through the delay element 25 of the group of address outputs in blocks 7i-7m is connected to the input of counter 3 and the inputs are connected and connected to the inputs of the second AQ ca counter 4 and trigger 26. The outputs of the decoder 10. A separate output of the decoder 3 is connected to the address inputs of the rarator 9 is connected to the combined per -Each information block 7i-7m and the highest control inputs of the third decoder 11. The decoder-information blocks fi-7m, the second unit has two groups of outputs. The outputs of the equalizing inputs of which are also combined in the first group are connected with the same name and are connected to the first input of the first control inputs of the second group of 16 and the output of the second 17 elements OR of the mutator 8 and the second inputs of the same name. The decoder 9 has a group of outputs that elements And the third group 13i-13m ..

Rye Macaw are connected to the BX ° fM per-outputs of the second group of the decoder 11 owl 121-12 “, and the second .12“ Н -, - 12 “groups 5Q ew with“ “control

elements I. The decoder 10 has separate inputs of the third group of the switch 8 and

output that is connected to the first second inputs of the same elements

the input of the first element And 21, and two groups and the fourth group -13 +

exits. The outputs of the first group of the decryptor in each input unit 5 () per.

torus 10 are connected to the control inputs-55 high and linear block 7a 28 by the elements of the same name And 12i-12n1 and mcj), respectively, the first

the second control inputs are single-input and output. 9

nominal input blocks of the first group, the second input and second output - the second in51-5sh. The outputs of the second group are decoded by the input and output of input 10 connected to the control inputs of the unit. The second output of block 28 is connected

to the input of the counter 30, the reset input of which is connected to the output of the OR element 29. The first and second inputs of this element are the first and second control inputs of the input unit, respectively. The output of the counter 30 is connected to the input of the trigger 31, the reset input of which is connected to the second input of the OR element 29. The output of the trigger 31 is connected to the third input of the element OR 29 and is the control output of the input unit.

In each information block 7 (Fig. 3), the first inputs of the first 32 and second 33 elements I. of the reception and control unit 35 and the input of the third element And 34 are combined and are a clock input of the information block. The second inputs of the block of 35 elements And 32 and 33 are respectively information, the first and second control inputs of the information block. The outputs of the elements 32 and 33 are connected respectively to the first and second inputs of the memory unit 36, the outputs of which are connected to the inputs of the third element And 34. The output of the element And 33, the outputs of the receiving unit 35 and -control, the outputs of the element And 34 and the inputs of the block group 36 memory are respectively the control output, information and address outputs and address inputs of the information block

ka-.

It should be noted that the spatial arrangement of the inputs and outputs of the input unit 5 in FIG. 2 and information block 7 in FIG. 3 clearly corresponds to the inputs and outputs of blocks 5i-5n and 7i-7m in FIG. 1.

The device operates as follows.

Information on the state of the remote dispersed objects of the first and second groups, respectively, is sent to the first information inputs of blocks 5i-5ni and 5ni +1 -5p via communication channels. The first group consists of m most important objects; the second group combines less important n2 (n-ni) objects. In the absence of information - changes in the state of the object - in the communication channel from it are constantly transmitted service code combinations alone with a minimum number of polarity reversals. The presence of changes in the state of objects is accompanied by the transfer of information code combinations with a large number of polarity reversals (change of O and D) per unit time. The structure of code messages from all objects is the same. Each input unit 5i-5n interfaces with the forward (demodulation) and reverse (modulation) communication channels and continuously analyzes the presence of information in the communication channel from the object by counting the number of changes in the polarity (edges) of the discrete signals. The analysis time Ta is a constant, the source is selected from the statistical information properties for all blocks 5i-5n, and it is continuously generated by the first counter 2 by dividing the reference frequency f of the clock generator 1. The division coefficient Cd (counter capacity 2) is equal to:

Cd Ta- f Ta / To

where m0 is the pulse repetition period of the gene: radiator 1.

The counter 2, at time intervals Ta, sets the signal edge counters 30 in the input units 5i-5n (Fig. 2) to the initial state each time. If during the time in the I-m (1 ni) or j-th (ni + 1} n) communication channels of the first or second groups, respectively, the presence of information is detected, i.e. the number of registered signal fronts exceeded the set threshold R, then a constant level 1 signal is generated at the control output of the corresponding input unit 5i (5j). Pulses from the output of the generator 1 also arrive at the elements I 22 and 23 and the pulse distributor 6, which generates m clock sequences shifted in phase relative to one another and ensuring the operation of information blocks 7i-7m. In the absence of signals 1, the presence of information at the control outputs of blocks 5i-5ni and 5п1 at the outputs of the elements And 13i-T3nii 13ni is formed. level O signals are triggered. These signals pass through the OR element 19, are inverted by the HE 27 element, and allow the clock pulses of the generator 1 to pass through the AND 23, OR 16 elements and the delay element 25 to the input of the ring counter 3,

The counter capacity is equal to the number of objects n, and the number of its binary cascades L is equal to 1od2n (if logan is a fractional number, then L log2n +1, where square brackets denote the integer part of the logarithm). Each state of counter 2 corresponds to a binary code of a communication channel number. This code is decrypted by the decoder 11, the outputs of which are combined into two groups and correspond to the channel numbers of the first and second groups. The signals from the outputs of the first and second groups of the decoder 11 are supplied respectively to the inputs of the elements And 13i-T3ni, 13ni + When the signals at both inputs of any element And T3i-13n coincide, for example

element And the third group 13i, which occurs when there is a signal G at the control output of the 51st input block, element 13i generates a signal 1, which passes through the element OR 19 and the inverter 27 and prohibits the further passage of clock pulses of the generator 1 through the element And 23 to counter 3. Counter 3 stops in the state corresponding to the number of the 1st communication channel. From this moment, the stage of searching for the free information block 7i-7m and connecting the input block () to it through the switch 8 5-i, ro begins. In occupied information blocks 7i-7m, binary codes of the numbers of input blocks 5i-5n connected to them are stored, in free ones, zero code combinations. This code is read in parallel to the decoder 10 at each pulse received by the distributor 6 to the clock input of the information block. In the presence of the e-th (1 e-t) free information block, the decoder 10 generates a signal with a duration of a clock pulse at its separate output, which, through the elements AND 21 and OR 17, is supplied to the second control inputs of the information blocks 7i-7m and to the OR element 16 In the 7th information block, after selection of the input control signal, the code of the number of the 1st communication channel received at the address inputs from counter 3 is recorded and stored. In addition, a pulse is generated at the control output of the 7th information block which d e is fed to the second input of the first group of control inputs of the switch 8. The simultaneous action of the pulse signal and a decoder 11 to l-th input of the second group of control inputs 8 of the commutator provides a connection 51 to the second input unit 7f-th information block. Meanwhile, the pulse from the output of the OR element 16 passes through the element 25, which provides a delay time Гз Т0 for reliable switching in the switch 8, and sets the counter 3 to the state corresponding to the number (i + 1) rro of the communication channel.

In case all information blocks are occupied, it is possible to connect input blocks 5i-5ni, which have a higher priority, to those information blocks that have already been connected to the input blocks of the second group 5sh +. From the moment a signal appears at the output of element 13, it acts through the element OR 18 to the first input of element And 22 and allows the pulses of generator 1 to pass through to counter 4.

Counter 4 has a capacity equal to the number of information blocks t. If in time t there is no free information block 7i-7m detected, then counter 4

will generate an output signal that is stored by the trigger 26. The output signal of the trigger 26 allows the passage through the element And 24 and the element OR 20 pulses from the outputs of the second group of the decoder 10,

0 which correspond to the numbers of the connected communication channels of the second group. When the first pulse appears at the output of AND element 24, it arrives at the input of OR element 17 and then performs actions similar to those described above in the case of the presence of free information blocks 7i-7m. The counter 4 and the trigger 26 pulse from the output element 25 of the delay. is reset. In the case when all information blocks 7i-7m are connected only to the input blocks of the first group 5i-5ni, which may occur when, counter 3 remains in the i-th state until at least one is free

5 one of the blocks 7i-7m.

After connecting 5 of the 1st input block in the 7th information block, reception and processing of information from the 1st object begins. In this case, the demodulated code messages are sent to the information input of the information block 7e and back through the switch to the second information input of the 51st input block. From the modulator of this block of information, the information begins to flow into the reverse communication channel to the 1st object, thereby providing informational feedback between. do object and device. Blocks 7i-7m carry out clock and loop phasing and verification of the received code combinations for compliance with the error-correcting code. Correctly received K-bit primary code combinations are read in parallel on

5 inputs of the first decoder 9. Since the working clocks of information blocks 7i-7m are phase-separated, the outputs of the same group of information blocks as well as address outputs from them form

0 common bus. Decoder 9 provides decryption results, the total number of which can be 2-1, through the elements And 121-12sh and 12ni + i 12n to the display elements and 14sh +1 -14P. The correct flow of information to these elements is ensured by their selection by supplying an enable signal to the control input of the corresponding element And 12i-12ni and 12p1 + 1-12p from the outputs

5

a decoder 10, which is currently decrypting the binary code of the number of the communication channel (input unit) recorded in the memory of the information unit 7i-7m. At the same time, the pulse from the output of the decoder 10 enters the second control input of the input unit of the same name 5i-5ni, 5ni + 1 -5p and puts it in its initial state. This ensures that the availability of information and the connection of those communication channels that are already connected to the information blocks 7i-7m are excluded from the analysis process. The first reset pulse is generated after mr0 after connecting the communication channel to the free information block 7i-7m, i.e. almost instantly compared with the information transfer rate in the communication channel and the analysis time Ta

As received correctly, message combinations due to information feedback are excluded from the transmission cycle from the entity. At the end of the transmission, rest codes begin to arrive, which are also decrypted by the decoder 9. The decryption signals of these combinations from the separate output of the decoder 9 are selected in the corresponding information block 7g-7gpI and erase the code of the connected communication channel in it. From this moment, the corresponding information unit 7i-7m becomes ready to connect another channel.

The connection of the input units 5ni + i-5p of the second group through the switch 8 to the information blocks 7i-7m is allowed only during periods of lack of information in the communication channels of the first group. In this case, the level O signals from the control outputs of all input blocks 51-5ш, entering the inputs of the OR-NOT 15 element, generates signal 1 at its output, which acts on the third inputs of the AND elements 13ni + i -13П and allows polling of the input blocks second group 5P1 4-1 5P. The counter 3 runs through the states corresponding to the numbers of the 1-n communication channels during the time nr0, after which the signals are interrogated at the control outputs of the blocks 5sh + 1-5p. The search for a free information block 7i-7m and the connection of input blocks 5ni +1 -5p to it is carried out similarly to the connection of blocks 5H5ni. With all of the information blocks 7i-7m occupied, the counter 3 keeps its state until at least one of these blocks is freed. As soon as information is detected

input units 5i-5n- |. the device again enters the mode of receiving and processing messages from the first group of objects, and the operation of the elements I1 ni + 3-1 Zn is blocked by 5 signaling their third inputs. Counter 3 in this case will calculate the values corresponding to the numbers of the (u + 1) -p communication channels without stopping. The objects of the second group, the information from which was only partially received, due to the switching of the information blocks to the input blocks 5i-5ni, get the opportunity to complete the transmission of their message only during periods of lack of information from the objects of the first group. In the proposed embodiment of the input unit 5 (Fig. 1), the number of edges of the received code packets is counted by a counter 30, which is excluded from the output of the linear block (modem) 28. By filling. In this case, the counter 30 generates a signal that puts the trigger 31 into state 1. This signal is output to the control output and, simultaneously, the counter 30 is set to the initial zero state through the OR element 29. The trigger is reset to state O by pulses arriving at the second control input from the decoder 10. Counter 30 is reset to the zero state from the OR element 29 by pulses from counter 2 (the first control input) and from the decoder 10 (second control input).

 In the information block 7 (Fig. 3), encoded messages are sent through the information input to the input of the receiving and monitoring block 35, in which clock and loop phasing is carried out, the received code combinations are checked for compliance with the error-correcting code, and the removal of redundant code bits and issuing K-bit combinations of the primary code for information outputs. The operation of block 35 is provided by clock pulses arriving at the clock input of the information block. The same clock pulses carry out clock selection of the recording permission signals and erase the code of the communication channel number in the memory unit 36, which are received respectively at the second and first control inputs to the I 33 and 32 elements. The pulses from the And 33 element are also output to the control the output output of the information block 7. The memory block 36 in the simplest variant can consist of L clocked memory triggers, pulses are sent to the input of each trigger on the corresponding bus of the address inputs of the information block.

5

0

5

0

0

The ink element And 34, the code of the communication channel number is read by a parallel code at the address outputs of the block with each clock pulse.

Compared with the prototype device, the proposed device allows more flexible use of the receiving information blocks 7i-7m. increase the coefficient of their useful use (load). Having information about the presence of messages on each communication channel from objects, the device provides connection to blocks of only those communication channels in which information is detected. Due to this, on the one hand, with the same number of objects, it is possible to reduce the number of the most element-intensive information blocks without reducing the speed and accuracy of displaying information about the state of objects in real time, On the other hand, with the same state n / m can improve performance compared to the prototype. So, for example, in the particular case when there is one free information block and the presence of information in one communication channel of the first group is detected, the gain in connection time and the start of processing the message is:

1 - (t H-shchTf / Tkr Ta + Tf

- 1-Щ (НТф / Ткр) 1 + | а / Тфгд Тф - average time spent on clock and cyclic phasing before the start of confident reception of code messages;

Tcr is a critical time interval after which a prototype device is allowed to connect one communication channel of the second group.

And finally, in the proposed device, there is a constant interface with the channel-forming equipment, which increases the reliability of the physical interface between it and the device. In addition, a significant decrease in the number of unproductive switching performed by the switch also contributes to an increase in its uptime and the device as a whole.

Claims (3)

The claims 1, An adaptive receiver of information from remote dispersed objects, containing a clock pulse generator, the output of which is connected to the input of the pulse distributor, a switch, the first inputs and outputs of which are connected respectively to the first output and input of each information channel, exit M Tf the pulse distributor is connected to the clock input of the information channels, the outputs of the first and second groups of each of which are connected to the corresponding the inputs of the first and second decoders, the first and second OR elements, the output of the first OR element through the delay element is connected to the input of the first counter, the outputs of which are connected 0 to the address inputs of each information channel and the inputs of the third decoder, the outputs of which are connected to the control inputs of the switch, the outputs of the group of the first decoder are connected to the corresponding inputs of the group of the corresponding elements of the first group, the outputs of the first group of the second decoder are connected to the inputs. the corresponding AND elements of the first group, the output of the second OR element is connected to the first input of the first OR element, the outputs of the And elements of the first group are connected to the inputs of the corresponding display elements, characterized in 5 that, in order to improve speed and reliability, a second, third and fourth group of AND elements, an OR-NOT element, an NOT element, a second group of display elements, AND elements, the third, are introduced into the negro, The fourth and fifth OR elements, a trigger, a third counter and input blocks, the information input and output of each of which are respectively the information input and output of the adaptive receiver, 5, the output of the second counter is connected to the first input of each input unit, the control input and output of each of which are connected respectively to the information output and input of the switch, the output of the second decoder is connected to the first input of the first AND element, the output of which is connected to the first input of the second OR element, whose output is connected by the second input of all information channels5 channels / the output of the first decoder is connected to the third inputs of all information channels, the outputs of the second group of the second decoder are connected to input inputs of the third OR element, inputs 0 corresponding elements AND of the second group and second inputs of the corresponding input blocks, the outputs of the group of the first decoder are connected to the corresponding inputs of the group of the corresponding elements of And the second group, the output of the third element OR is connected to the first input of the second element And, the output of which is connected to the second input of the second element OR, the input of the first counter is combined with the first inputs of the third counter and trigger, the output of the trigger is connected to the second input of the second element AND, the output of the third counter is connected to the second input ohm of the trigger, the output of the fourth OR element is connected to the second input of the first AND element and through the NOT element to the first input of the third AND element, the output of which is connected to the second input of the first OR element, the output of the clock is connected to the second input of the third AND element and the first the input of the fourth AND element, the output of which is connected to the second input of the third counter, the outputs of the AND elements of the third and fourth groups are connected to the corresponding inputs of the fourth OR element, the outputs of the AND elements of the third group are connected to the corresponding inputs of the fifth OR element, the output of which is connected to the second input of the fourth AND element, the outputs of the third decoder are connected to the first inputs of the AND elements of the third and fourth group, the outputs of the input blocks are connected to the second inputs of the corresponding AND elements of the third and fourth group, the inputs of the OR NOT combined with the second inputs of the AND elements of the third group of the same name, the outputs of the AND elements of the second group are connected to the inputs of the corresponding display elements of the second group. 2. The receiver according to claim 1, with the exception that each input block contains a linear block, counter, trigger and OR element, the first and second inputs and outputs of the linear block are respectively information inputs and block outputs, the first, second and third inputs of the OR elements are respectively the first and second inputs and the output of the block, the output of the OR element is connected to the counter reset input, the input of which is connected to the second output of the linear block, the output is to the trigger input, the reset input of which is connected to the second input of the OR element, tr Tille input coupled to an output latch. 3. The receiver according to claim 1, distinguished by the fact that each information channel contains a memory unit And elements and a reception and control unit, the first inputs of the first and second elements And and the reception and control unit are connected to the input the third element And are the clock input of the information channel, the second inputs. of the receiving and monitoring unit, the first and second elements of And are the first, third and second inputs of the information channel, respectively, the outputs of the first and second elements And are connected respectively to the first and second inputs of the block in memory the outputs of which are connected to the corresponding inputs of the third element And, the output of the second element And, the outputs of the reception and control unit and the outputs of the third element I. The inputs of the memory block group are the first output, outputs of the first group and second group, address inputs of the information channel, respectively. . 1 1 ulr. the yoke 1 inf efoa / in &. Јifxc yt / s fyn /. Јt / ri f . . 4ulr # 9 -2UR- bЈg0e s fret yygo 6x Phi. 3 . 2uHf. 2 ™% -, & NG00 ygo F. 2 tsuge. hgg