RU1807508C - Adaptive receiver of information from dispersed entities - Google Patents

Abstract

The invention relates to telemechanics, and may find application in automated process control systems. The purpose of the invention is to increase speed and reliability. Through the communication channels to the input units 3i-3n, sporadically NocfynaeT information from n objects. Using timer 1, count-off time intervals Ta are continuously generated during which analysis of the presence of information in the communication channels is carried out in blocks 3i-3rj. The counter 15, whose capacity is equal to n, through the decoder 9 sequentially polls blocks 3i-3n, which, if information is detected in the communication channel during polling, generates a signal 1. The signal 15 stops by this signal until the communication channel is connected with the availability of information from the input unit through the switch 6 to the free information channel 5i-5m (). Received encoded messages are processed in the information channels 5i-5m and decrypted by a common decoder 7. From the output of which the signals selected by the elements And 10i-10n are sent to the corresponding display elements 111-11P. At the end of the reception and processing of messages, information channels 5i-5m are freed up to receive information from other objects. 3 ill. (/) WITH

Description

The invention relates to telemechanics and may find application in automated process control systems and data transmission equipment.

The purpose of the invention is to increase speed and reliability.

In FIG. 1 shows a functional diagram of the proposed device; in FIG. 2 - input unit, in FIG. 3 - information channel.

The device comprises a clock generator 1, a timer 2, input blocks, a 4-pulse distributor, information channels 5i-5m, a switch 1 6, a first 7, a second 8 and a third 9 decoders, a group of elements 10i-1 On, elements 111 to 11 of the display , the first 12 and second 13 elements AND, element 14 delay, counter 15, elements AND 16, 17, the element is NOT 1-8.

The composition of each input block (Fig. 2) includes a linear block 19, an OR element 20, an And 21 element, a trigger 22, and a counter 23.

Each information channel 5i-5m (Fig. 3) contains from the first to the third elements And 24-26, a receiving and monitoring unit 27 and a memory unit 28.

The output of the clock generator 1 is connected to the inputs of the timer 2, the pulse distributor 4, and the element 17. The output of the timer 2 is connected to the first control input of each input unit 3i-3n, the first information inputs and output of which are the inputs and outputs of the device, respectively. The second information input and output of each input unit is connected respectively with the same information output of the second group and the input of the first group of inputs of the switch 1, Distributor 4 has m outputs (), each output is connected to the clock input of the same information channel 5i.-5m. each of which has an information input, first and second control inputs, a control output, a group of address inputs, a group of address and a group of information outputs. The information input of block 5i-5m is connected to the same output of the first group of information outputs and the same input of the second group of information inputs of switch 6, and the control output is connected to the same input of the first group of control inputs of the switch. The same outputs of the groups of information outputs of blocks 5i-5m are combined and connected to the inputs of the first decoder 7, and the same outputs of the groups of address outputs of blocks 5t-5m are combined and connected to the inputs of the second

of the decoder 8, the output of the decoder 7 is connected to the combined first control inputs of the information channels, the second control inputs of which also

combined and connected to the output of the first element And 16 and the first input of the element OR 12. The decoder 7 has a group of outputs that are connected in parallel to the inputs of the group of elements And 10i-10n. The outputs of the decoder 8 are connected to the control inputs of the elements And of the same name and the second control inputs of the same input blocks 3i-3n. The outputs of each of the elements And 10i-10n are connected to the corresponding inputs of the same elements 111-11 p display. The control outputs of the input units 3i-3n through the second element OR 13 connected. neny with input element NOT 18 and the first

0 the input of the element And 16., to the second input of which is connected a separate output of the second decoder 8. The output of the element NOT 18 is connected to the first input of the second element And 17, the output of which is connected to the second

5 by the input of the OR element 12. The output of the OR element 12 through the delay element 14 is connected to the input of the counter 16, the outputs of which are connected to the address inputs of each information channel 5i-5m and through the third

0 decoder 9. - to the inputs of the second group of control inputs of the switch 6 and third. the control inputs of the same input blocks 3i-3n.

In each input unit 3i-3n, the first

5, the input and output of the linear block 19 are respectively the first information input and output, and the second input and second output are the second information input and output of the input block. Second

0, the input of block 19 is also connected to the input of the counter 23, the reset input of which is connected to the output of the OR element 20. The first and second inputs of this element are the first and second control inputs of the input block, respectively. The output of the counter 23 is connected to the input of the trigger 22, the reset input of which is connected to the second input of the OR element 20. The output of the trigger 22 is connected to the third input of the element OR 20 and

0 to the second input of AND element 21, in which the first input is the third control input, and the output is the control output of the input unit, respectively.

In each news channel

5 5i-5m, the first inputs of the first 24 and second 25 AND elements, the reception and control unit 27, and the input of the third And 26 element are combined and are a clock input of the information channel. The second inputs of block 27 and elements And 24 and 25 are respectively

information, first and second control inputs of the information channel. The outputs of the elements 24 and 25 are connected respectively to the first and second inputs of the memory unit 28, the outputs of which are connected to the inputs of the third And 26 element. The output of the And 25 element, the outputs of the reception and control unit 27, the outputs of the And 26 element and the inputs of the group of the memory unit 28 are respectively the control input, information and address outputs and address inputs of the information channel.

It should be noted that the spatial arrangement of the inputs and outputs of the input unit 3 in FIG. 2 and information channel 5 in FIG. 3 unambiguously corresponds to the inputs and outputs of blocks 3i-3n and 5i-5m in .ig. 1,

The device operates as follows.

The first information inputs of blocks 3i-3n from communication channels sporadically receive information on the state of n dispersed objects. In the absence of information - changes in the state of the object - signals are constantly transmitted in the communication channel from it. Only one polarity is O or 1 or service code combinations are at rest with a minimum number of polarity reversals. The presence of changes in the state of objects is accompanied by the transmission of information code combinations, while the structure of code messages from all objects is the same. Each input unit 3i-3n interfaces with the forward (demodulation) and reverse (modulation) communication channel and continuously analyzes the presence of information in the communication channel from the object by counting the number of changes in signal polarity. The analysis time Ta is a constant, the source is selected from the statistical properties of information for all blocks 3i-3n, and is generated by timer 2 by dividing the reference frequency f of the clock generator 1. The division coefficient Cd is equal to:

Kfl Ta-f

Jl

Then

where TO is the pulse repetition period of the generator 1 ..

After each time interval Ta, the analyzers of the presence of information in the input units are set to their initial initial state .. The output pulses of the generator 1, in addition, are fed to the inputs of the element And 17 and the distributor 4. The distributor 4 generates clock sequences supplying

information channels 5i-5m. In the absence of signals 1, the presence of information at the control outputs of the blocks and, accordingly, at the output of the element OR 13 by the element HE 18, signal 1

5 allowing the passage of the clock pulses of the generator 1 through the elements And 17, IL And 12 and the element 14 of the delay at the input of the ring counter 15. The capacity of the counter 15 is equal to p, and the number of binary stages L

0 is determined by the ratio:

(Submitted 1od2P - integer,

L j

With 1od2p +1 logan-fractional number,

5 Iog2n - the whole part of the logarithm. -. Each counter state 15 corresponds to a binary code of a communication channel number. This code is decrypted by a decoder 9 having output buses, by which the signals of the position number of the communication channel are sent to the interrogation of the corresponding input unit 3i-3n. If information is recorded in the 1st communication channel in the 1st (1 i p) input unit, then upon receipt of a polling signal at its third control input, signal 1 will pass through its control output, which passes through the OR element 13 to the element And 16 and the inverter 18. The signal O. at the output of the element

0 18 prohibits the further passage of the clock pulses of the generator 1 through the AND element 1.7, and the counter 15 remains in the state corresponding to the ith communication channel. From this moment, the stage of searching for the free information channel 5i-5m and connecting to it via the switch 6 the second information outputs and the input f-ro of the input unit begins. If the information channel is busy, then it stores the binary code of the number of the input unit 31-3p connected to it, if free, the zero code combination. This code is read in parallel to the decoder 8 for each pulse 5i-5m from the output of the distributor 4 received at the clock input of the information channel 5. If there is j-ro (1 m) of a free information channel, the decoder 8 generates a signal with a duration of

0 clock pulse, which through the open element And 16 is fed to the second control inputs of the information channels 5i-5m and to the input of the OR element 12. This pulse is selected by the clock

5 in the j-th information channel, through the group of address inputs, the i-ro number code of the input block is recorded in the j-th information channel. In addition, at the control output j-ro of the information channel,

the pulse that arrives at the jth input of the first group of control inputs of the switch 6. The simultaneous action of this pulse and the signal from the decoder 9 at the 1st input of the second group of control inputs of the switch 6 provides the connection of the 1st input block to the jth information channel. Meanwhile, the output pulse of element V116 passes through the OR element 12 to the delay element 14. Shortly after the delay time rz, r0, element 14 generates a pulse, which sets counter 15 to the state corresponding to the (1 + 1) th communication channel, after which all operations described above for the 1st channel are repeated.

If all information channels 5i-5m are occupied, the counter 15 remains in the state corresponding to the number of the 1st communication channel until fex until at least one of the 5H5t channels is freed. After connecting the 1st input block in the j-th information channel, reception and processing of information from the object begins. In addition, the demodulated code messages are sent through the switch 6 to the second control input of the 1st input unit and through its modulator to the reverse communication channel to the 1st object. Thus, from now on, informational feedback between the ith object and the device is provided. Clock and loop phasing are carried out in the information channel and the correspondence of the received code combinations to the error-correcting code is checked. With each correct reception, the code combinations of the k-bit code are read in parallel code to the input of the first decoder 7. Since the working clocks of the information channels are spaced out of phase, the buses of the same group of information outputs of the information channels 5i-5m are the same as the address The outputs from them form a common c-bit bus. The decoder 7 outputs the decryption results via the And UT-1 On elements to the display elements 11i-11n. The correct passage of information to elements 111-11 n is ensured by the selection of this element by supplying an enable signal to the control input of the corresponding element And 10i-10n from the outputs of the group of the second decoder 8. which decodes the binary code of the communication channel number (input unit) at a given time ) recorded in the memory of the information channel 5i-5m. At the same time, the pulse from the output of the decoder 8 enters the second control input of the input unit of the same name and resets the analyzer of the presence of information in its initial state. This ensures the exclusion from the process of analyzing the presence of information and connecting those communication channels that are already connected to the information channels 5i-5m. The first reset pulse is generated shortly after connecting the communication channel 0 to the free information channel 5i-5m, i.e. almost instantly in comparison with the information transfer rate in the communication channel.

At the end of the transmission of information from the 5th object, rest codes are received, which are also decrypted by the decoder 7. The pulses of the decryption of these combinations from the output of the decoder 7 are fed to the combined first control inputs of all information channels 5i-5m, in which they are selected and erased connected channel number code. This means that the Corresponding information channel 5i-5m is ready for the connection of the next communication channel.

In the proposed embodiment of the input block 3 (Fig. 2), the counting of the edges of the received code packets is carried out by a counter 23 connected to the output 0 of the linear block (modem) 19. When the counter is full, it generates a signal that translates the memory trigger 22 state 1. The signal of the presence of information in the communication channel is formed by the And 21 5 elements when a polling signal is supplied to its input from the third decoder 9. The counter 23 is reset (set) from the OR element 20 when the signals from timer 2 are applied to its inputs ( first control input), decryption-0 then 8 (second control input), as well as from the output of trigger 22. The trigger 22 is switched to state O by pulses from the decoder 8.

. In the information channel 5 (Fig. 3), encoded messages are received through the information input to the reception and control unit 27 (2), in which clock and loop phasing is carried out, checking the received code combinations for compliance with the error-correcting code, sn the use of redundant bits of code and the issuance of combinations of the primary code for information outputs. The operation of the block 27 is provided by clock pulses, 5 arriving at the clock input. The same clock pulses carry out clock selection of the placement signals for pi. si and erase the code of the number of the communication channel in the block 28 of the memory, respectively, received by the second and first control

the inputs to the elements And 25 and 24, The pulse from the output of the And 25 element also goes to the control input of the information channel 5. The memory block 28 in the simplest version can consist of K memory triggers, pulses are sent to the input of each trigger via the corresponding address bus information channel inputs. Through element And 26, the code of the communication channel number is read by a parallel code at the address outputs with each clock pulse.

Thus, in comparison with the prototype device, the proposed device reduces the time to search for a communication channel with the availability of information and connecting it to a free information channel by a factor of 1-n. In addition, the device is constantly coupled with channel-forming equipment, which increases the reliability of collecting information from dispersed objects.

Claims (2)

SUMMARY OF THE INVENTION 1. An adaptive receiver of information from dispersed objects, comprising a clock pulse generator, the output of which is connected to a timer input and a pulse distributor, the outputs of which are connected to the clock inputs of information channels, the first input and output of each of which are connected respectively to the first outputs and inputs of the switch , a counter whose outputs are connected to the inputs of the first decoder and the group inputs of each information channel, the outputs of the first decoder are connected to the corresponding the control inputs of the switch, the outputs of the first and second groups of each information channel are connected to the corresponding inputs of the second and third decoders, respectively, the outputs of the group of the second and third decoders are connected respectively to the input of each element AND of the group whose outputs are connected to the inputs of the corresponding display element, the first element OR , the output of which through the delay element is connected to the counter input, the second OR element, characterized in that, in order to increase speed and reliability , AND elements are entered into it, the element is NOT and input blocks, the first input and output 5 of each of which are respectively the input and output of the adaptive receiver, the timer output is connected to the second inputs of the input blocks, the second outputs of which are connected to the corresponding inputs of the second element OR, whose output is connected to the first input of the first AND element and through the element NOT to the first input of the second AND element, whose output is connected to the first input of the first element 5 OR, the outputs of the first decoder are connected to the third inputs of the corresponding input blocks, the third outputs and fourth inputs of which are connected respectively with the second inputs and outputs of the switch, 0 the output of the second decoder is connected to the second input of the second AND element, the output of which is connected to the second input of the first OR element and the second input of each information channel, the output of the third 5 decoders connected to the third input each information channel, outputs groups of the second decoder are connected to . the fifth inputs of the corresponding input blocks. 0 2. The receiver according to claim 1, distinguished by the fact that each input block contains a linear block, a counter, a trigger, an AND element and an OR element, the first and second inputs and outputs of the linear block are respectively the first the input and output and the fourth input and third output of the block, the first and second inputs of the OR element are the second and fifth inputs of the block, respectively, the first input and output of the AND element 0 are respectively the third input and the second output of the block, the second input of the AND element is connected to the trigger output and the third input of the OR element, the output of which is connected to the counter reset input, the input of which 5 po.ro is connected to the second output of the linear block, the counter output is connected to the input a trigger whose reset input is combined with the second input of the OR element, Tupr. Јho t and and p ЈfOC 4ich & Јi / reЈ &/Yu(" 2t 3. DD Reg. Benefit & 2  smf. fvrac 2 he is up to. e ™ and # in. 2uf Јgo # ly f faoff  , & / & A ( FIG. 3