SU1247875A1 - Device for checking two-step decoder - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used to control digital equipment. The aim of the invention is to reduce hardware costs. The goal is achieved by the fact that in a two-stage decoder to control the working decoder of one stage, an additional decoder is not introduced for this purpose, but a working decoder of another stage, which is currently not in use. To this end, the cycle of operation of the device is divided into two parts. The first part of the cycle controls the operation of the decoders, two stages by comparing the signals at their outputs using a comparison circuit, in the second part of the cycle, the selected decoder is polled and the circuits forming the resolution signals of the sample of the controlled decoder are monitored. In the first part of the cycle, a signal from the two stages of the decoder being monitored is permitted using a signal arriving at the gate input of the device. The same signal triggers a pulse shaper, which, with a non-comparison signal at the output of the comparison circuit, generates a malfunction signal. After the signal at the gating input of the device has expired, the sampling of that stage of the decoder being monitored is enabled, which1 is determined by the signal at the input of the device's selectable step number. Sig. The output of the pulse shaper, delayed by the delay element, generates a signal accompanying the output of the decoder (service signal) or a device fault signal depending on whether or not the decoder stages are enabled. 2 Il. C w O) th 4a M CX JV

Description

The invention relates to automation and computing and can be used to control digital equipment.

The purpose of the invention is to reduce hardware costs.

FIG. 1 shows a functional diagram of the device together with a controlled decoder; Fig 2 is a timing diagram of the operation of the device.

A device for controlling a two-stage decoder and a controlled decoder include a controlled decoder 1 containing the first 2 and second 3 stages of decryption, the first element is NOT A, the first and second elements OR 5 and 6, the comparison circuit 7, the pulse shaper 8, the delay element 9, the second the element is NOT 10, the elements are AND 11-13, the third element is OR 14, the output 15 is a device fault, the output 16 is the device health, the input 17 is the number of the device’s selectable stage, the gate 18 is the device.

The device for controlling a two-stage decoder operates as an elec- trode.

The information inputs of steps 2 and 3 of the controlled decoder 1 receive N-1 lower order bits of the address word. The senior Nth bit of the address word is fed to the input 17 of the number of the device’s selectable step and through the first element NOT 4 and the first element OR 5 enters the input of the sampling resolution of the first stage 2 of the monitored decoder 1, and through the second element OR 6 enters the input enable sampling of the second stage 3 of the controlled depfrarator 1. The code tracking gate enters through the device input 18 to the inputs of the OR 5 and 6 elements, and sets both stages 2 and 3 to the working state. When working properly at the same outputs of both stages 2 and 3, corresponding to the input

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the element NOT 10 is fed to one of the inputs of the element 11 and logical 0. In this case, the pulse from the output of the imaging unit 8 pulses does not pass through the element 11. The imaging device 8 pulses forms a tracking pulse from the tracking strobe whose leading edge is delayed relative to the leading edge of the strobe exceeding the propagation delay time of the code in decoders 2 and 3, the comparison circuit 7 and the HE element 10, and whose falling edge coincides with the falling edge of the strobe.

In the case when one of the steps 2 and 3 of the decoder 1 is faulty, it is obvious that the codes at their outputs will be unequal, and there is no logical 1 at the output of the srain scheme. At the same time, the signal from the output of the HE element 10 does not prohibit the pulse from the driver 8 pulses, which passes. also - through the element OR 14 as a signal of malfunction.

At the end of the tracking strobe, at the inputs of a sample of steps 2 and 3, the signals are set corresponding to the value of the highest (N-ro) bit

 encrypted code. In this case, all the outputs of one of the decoders are set to the zero (inactive) state, and the combination of signals at the outputs of the other decoder will correspond to the m-fallen (N-1) sizes of the input code. At the output of the comparison circuit 7, there is no equality signal and, therefore, the element And 13 is closed, and the element And 12 is open for

40 passing the pulse from the output of the delay element 9. The delay time is determined in the same way as the front-front time in the driver 8 pulses. Impulse output element

45 9 the delay enters And 12, as does the tracking strobe for the decrypted code.

If in one of the stages 2 and 3 of the decoder 1 there is not (N-1) -discharge code at the input, the Dodge-50 is operational according to the lines associated with

we have the same signal, which are compared in Scheme 7 i + i)

Note 5 is designed for i-bit codes. If the codes received on the first and second groups of inputs of the comparison circuit 7 are the same, then the output of the comparison circuit 7 generates an equality signal (logical 1), which

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the element NOT 10 is fed to one of the inputs of the element 11 and the logical 0. In this case, the pulse from the output of the driver 8 pulses does not pass through the element 11. The driver 8 of the pulses forms a pulse from the tracking strobe whose leading edge is delayed relative to the leading edge of the gate for a time exceeding the propagation delay time of the code in decoders 2 and 3, the comparison circuit 7 and the HE element 10, and whose falling edge coincides with the falling edge of the strobe.

In the case when one of the stages 2 and 3 of the decoder 1 is faulty, it is obvious that the codes at their outputs will be unequal and there is no logical 1 at the output of the srain circuit. At the same time, the signal from the output of the HE element 10 does not prohibit the passage of a pulse from the driver of 8 pulses which also passes through the element OR 14 as a fault signal.

At the end of the tracking strobe, at the inputs of a sample of steps 2 and 3, signals are set that correspond to the value of the most significant (N-ro) digit of the code to be encrypted. In this case, all the outputs of one of the decoders are installed in the TC in the zero (inactive) state, and the combination of signals at the outputs of the other decoder will correspond to the m dropped (N-1) bits of the input code. At the output of the comparison circuit 7, there is no equality signal and, therefore, the element And 13 is closed, and the element And 12 is open for

0 pulse passing from the output of delay element 9. The delay time is determined in the same way as the leading edge time in the driver 8 pulses. Impulse output element

5 9 delays flow through AND 12, as well as the tracking strobe for the decrypted code.

If in one of the stages 2 and 3 of the decoder 1 there is a non-entry sample, in the absence of the strobe, the outputs of both stages will be in the same state (either in the inactive or with the same outputs that are excited),. In this case, at the output of the comparison circuit 7, the equality signal which opens the element And 13 and closes

3

element And 12. The pulse from the output of the delay element 9 will go to the output 15 of the device through the elements And 13 and OR 14 as a signal of the device malfunction.

Thus, if there is a fault in steps x 2 and 3 when decoding (N-1) input bits, an error is detected during the pulse from the output of the taper 8. If the fault occurs along the sample signal line, then it is detected the operating time is impulc k from the output of delay element 9.

Claims (1)

Invention Formula A device for controlling a two-stage decoder containing a comparison circuit and a first AND element, wherein the equality output of the comparison circuit is connected to the first input of the first element AND, the first group of inputs of the comparison circuit is connected to the output group of the first stage of the controlled decoder, hardware costs, it contains a pulse driver, a delay element, two NOT elements, three OR elements, a second and a third AND elements, the outputs of the first and The second OR elements are connected respectively to the resolution inputs of the first and second steps of the monitored decoder, the input of the device’s selectable step number is connected to the first input of the second OR element and the first HE input, the output of which is connected to the first input of the first OR element, the gate input of the device is connected to the second the inputs of the first and second elements OR and the input of the pulse generator, the output of which is connected to the input of the delay element and the first input of the second element And, the output of which Connected, with the first input of the third element OR, the output of which is the output of the device malfunction, the output of the delay element is connected to the second input of the first AND element and the first input of the third And element, the output of which is the health output of the device, the equality output of the comparison circuit the second element is NOT connected to the second inputs of the second and third elements AND, the output of the first element AND is connected to the second input of the third element OR, the second group of inputs of the comparison circuit is connected to the group of outputs of the second stage to controlled by the decoder. Compiled by V.Grechnev Editor L.Avramenko Tehred ELizhmar Proof.Muyka For ;; G4127U49 TIR Already 671Subscription VNIIPI State Committee Li.uf for cases of inventions and discoveries 113035, Moscow, Zh-35, 4/5 Raushsk nab. Pro 3 water printing enterprise, Uzhgorod, st. Project, 4